XRT91L80(2005-03) 查看數據表（PDF） - Exar Corporation

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XRT91L80
(Rev.:2005-03)

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

xr

REV. P1.0.4

PRELIMINARY

XRT91L80

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

2.0 RECEIVE SECTION

The receive section of XRT91L80 includes the differential limiting amplifier inputs RXIP/N, followed by the

clock and data recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high

speed Non-Return to Zero (NRZ) serial data at 2.488/2.666 Gbps through the differential limiting amplifier input

interfaces RXIP/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming

scrambled NRZ data stream. The recovered serial data is converted into 4-bit-wide 622.08/666 Mbps parallel

data and presented to the RXD[3:0]P/N LVDS parallel interface. A divide-by-4 version of the high-speed

recovered clock RXCLKP/N, is used to synchronize the transfer of the 4-bit RXD[3:0]P/N data with the receive

portion of the upstream device. Upon initialization or loss of signal or loss of lock the 155.52/77.76 MHz (166/

83.3 MHz) external reference clock is used to start-up the clock recovery phase-locked loop for proper

operation. A special loop-back feature can be configured when RLOOPP is used in conjunction with de-jittered

loop-time mode that allows the re-transmitted data to comply with ITU and Bellcore jitter generation

specifications.

2.1 Receive Serial Input

The receive serial inputs are applied to RXIP/N. The receive serial inputs should be AC coupled to an optical

module or an electrical interface. A simplified block diagram is shown in Figure 4.

FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK

RXIP

RXIN

OC-48

Transceiver

0.1µF

0.1µF

Optical Module

Optical Fiber

NOTE: Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors

are not necessary and can be excluded.

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