XRT91L80(2005-03) 查看數據表（PDF） - Exar Corporation

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XRT91L80
(Rev.:2005-03)

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

XRT91L80

PRELIMINARY

2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER

xr

REV. P1.0.4

2.2 Receive Clock and Data Recovery

The clock and data recovery unit accepts the high speed NRZ serial data from the differential CML receiver

and generates a clock that is the same frequency as the incoming data. The clock recovery utilizes the

REFCLKP/N to train and monitor its clock recovery PLL. Initially upon startup, the PLL locks to the reference

clock. Once this is achieved, the PLL then attempts to lock onto the incoming receive data stream. Whenever

the recovered clock frequency deviates from the local reference clock frequency by more than approximately

500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock. When this condition

occurs the PLL will declare Loss of Lock and the LOCKDET_CDR signal will be pulled low. A Loss of Lock

condition will also be declared when the external LOSEXT is asserted. Whenever a Loss of Lock/Loss of

Signal event occurs, the CDR will continue to supply a receive clock (based on the local reference) to the

upstream framer device. When the DISRD control is enabled, receive parallel output data will be forced to an

all zeroes condition for the entire duration that a LOS condition is detected. This acts as a receive data mute

upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the

LOSEXT becomes inactive and the recovered clock is determined to be within 500 ppm accuracy with respect

to the local reference source, the clock recovery PLL will switch and lock back onto the incoming receive data

stream and the lock detect output (LOCKDET_CDR) will go active.

2.3 Loss Of Signal

XRT91L80 supports external Loss of Signal detection (LOS). The external LOS function is supported by the

LOSEXT input. The TTL input is coming from the optical module through an output usually called “SD” or

“FLAG” which indicates the lack or presence of optical power. Depending on the manufacturer of these devices

the polarity of this signal can be either active low or active high. The LOSEXT and POLARITY inputs are

Exclusive NOR’ed to generate the external loss control signal with the correct polarity. Whenever an external

LOS is detected, the XRT91L80 will automatically output a high level signal on the LOSDET output pin as well

as update the control registers whenever the host mode serial microprocessor interface feature is active.

2.4 Receive Serial Input to Parallel Output (SIPO)

The SIPO is used to convert the 2.488/2.666GHz serial input data to 622/666MHz parallel output data which

can interface to a SONET Framer/ASIC. The SIPO bit de-interleaves the serial input data into a 4-bit parallel

output to RXD3P/N. A simplified block diagram is shown in Figure 5.

FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF SIPO

RXD0P/N

4-bit Parallel LVDS Output Data

b03 b02 b01 b00

RXD1P/N

b13 b12 b11 b10

RXD2P/N

RXD3P/N

b23 b22 b21 b20

b33 b32 b31 b30

RXCLKP/N

622MHz

2.488GHz

b33 b23 b13 b03 b32 b22 b12 b02 b31 b21 b11 b01 b30 b20 b10 b00 RXIP/N

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