XRT91L80(2005-03) 查看數據表（PDF） - Exar Corporation
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XRT91L80 Datasheet PDF : 41 Pages
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REV. P1.0.4
TRANSMITTER SECTION
NAME
LEVEL
VCXO_LOCKEN
LVTTL
CPOUT
LOOPBW
-
LVTTL
TXPCLKOP
TXPCLKON
LVDS
TXCLKO16P
TXCLKO16N
LVDS
TRITXCLKO16
LVTTL
LOCKDET_CMU
LVTTL
OVERFLOW
LVTTL
PRELIMINARY
XRT91L80
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
TYPE
I
O
I
O
O
I
O
O
PIN
DESCRIPTION
P3 De-Jitter PLL Lock Detect Enable
Hardware Mode This pin enables the VCXO lock detect Pin N8
to be active.
"Low" = VCXO_LOCK disabled
"High" = VCXO_LOCK enabled
This pin is provided with an internal active pull-down.
P8 Charge Pump Output (for external VCXO)
The nominal output of the charge pump is 250µA
M7 CMU Loop Bandwidth Select
Hardware Mode This pin is used to select the bandwidth of the
clock multiplier unit of the transmit path to a narrow or wide
band.
"Low" = Narrow Band (1x)
"High" = Wide Band (4x)
This pin is provided with an internal active pull-down.
P10 Transmit Clock Output (622/666 MHz)
P11 This clock can be used for the downstream device to generate
the TXDI data and TXCLK. This enables the downstream
device and the OC-48 transceiver to be in synchronization.
N10 Auxillary Clock
N11 155.52(166)MHz auxillary clock derived from CMU output. This
clock can also be used for the downstream device as a refer-
ence for generating the TXDI data and TXCLK. This enables
the downstream device and the OC-48 transceiver to be in syn-
chronization.
M12 Tri-State Enable
Hardware Mode This pin is used to tri-state the auxillary clock.
"Low" = TXCLKO16 Enabled
"High" = TXCLKO16 Tri-State
This pin is provided with an internal active pull-down.
N2 CMU Lock Detect
This pin is used to monitor the lock condition of the clock multi-
plier unit.
"Low" = CMU Out of Lock
"High" = CMU Locked
M13 Transmit FIFO Overflow
This pin is used to monitor the transmit FIFO status.
"Low" = Normal Status
"High" = Overflow Condition
7
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