XRT91L80IB 查看數據表（PDF） - Exar Corporation
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XRT91L80IB Datasheet PDF : 45 Pages
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REV. P1.1.0
HARDWARE COMMON CONTROL
NAME
LEVEL
TYPE
RLOOPS
LVTTL,
I
LVCMOS
RLOOPP
LVTTL,
I
LVCMOS
DLOOP
LVTTL,
I
LVCMOS
PRELIMINARY
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PIN
DESCRIPTION
C10 Serial Remote Loopback
The serial remote loopback mode interconnects the receive
serial data input to the transmit serial data output. If serial
remote loopback is enabled, the 4-bit parallel transmit data
input is ignored while the 4-bit parallel receive data output is
maintained.
"Low" = Disabled
"High" = Serial Remote Loopback Mode Enabled
NOTE: DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature.
This pin is provided with an internal pull-down.
A11 Parallel Remote Loopback
The parallel remote loopback mode allows the serial data input
stream to pass through the clock and data recovery circuit and
looped-back at the parallel interface to the serial output port.
The 4-bit parallel transmit data input is ignored while the 4-bit
parallel receive data output is maintained.
"Low" = Disabled
"High" = Parallel Remote Loopback Mode Enabled
NOTE:
DLOOP and RLOOPS should be disabled when
RLOOPP is enabled. The internal FIFO should also be
flushed using FIFO_RST pin or register bit when
parallel remote loopback is enabled/disabled.
This pin is provided with an internal pull-down.
B6 Digital Local Loopback
The digital local loopback mode interconnects the 4-bit parallel
transmit data and parallel transmit clock input to the 4-bit paral-
lel receive data and parallel receive clock output respectively
while maintaining the transmit serial data output. If digital local
loopback is enabled, the receive serial data input is ignored.
"Low" = Disabled
"High" = Digital Local Loopback Mode Enabled
NOTE: DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature.
This pin is provided with an internal pull-down.
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