WM8146 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8146 Datasheet PDF : 17 Pages
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WM8146
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DIGITAL POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP. If INVOP=0, negative-going
input video will give negative-going digital output. If INVOP=1, negative-going video will give positive-
going digital output.
D2 = D1
… (INVOP=0)
D2 = 4095 – D1 … (INVOP=1)
DIGITAL CONTROL AND I/O FUNCTIONS
OUTPUT DATA
Data appears on the pins OP[7:0] and changes after every negative-going MCLK edge, as shown in
Figure 9 .
MCLK
OP[7:0]
tPD
A
B
Figure 9 WM8146 Output Timing
A = d11, d10, d9, d8, d7, d6, d5, d4
Pin OP[7] to OP[0]
B = d3, d2, d1, d0, 0, CC[1], CC[0], OVRNG
Pin OP[7] to OP[0]
Where
CC1/CC0: These bits show from which channel the current output was taken. 00 = RED,
01 = GREEN, 10 = BLUE.
OVRNG: This bit indicates if the current output pixel has exceeded the maximum or minimum range
during processing. 1 = out of range, 0 = within range.
CONTROL INTERFACE
The internal control registers are programmable via the serial digital control interface.
REGISTER WRITE
The serial interface involves three dedicated pins, SCK, SDI, SEN (refer to Figure 10). A six-bit
address is clocked in through SDI MSB first followed by an eight-bit data word, also MSB first. Each
bit is latched on the rising edge of SCK. Once the data has been shifted into the device, a pulse is
applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have
address bit a4 equal to 0.
SCK
SDI
SEN
a5 0 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0
Address
Data Word
Figure 10 Register Write Timing
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock
(VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces
WOLFSON MICROELECTRONICS LTD
PP Rev 1.1 January 2000
10
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