WM8146 查看數據表（PDF） - Wolfson Microelectronics plc

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WM8146

12-bit (8+4-bit) Linear Sensor Image Processor

Wolfson Microelectronics plc 

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DEVICE DESCRIPTION

WM8146

GENERAL OPERATION

A block diagram of the device showing the signal path is presented on Page 1.

The WM8146 samples the three inputs (RINP, GINP and BINP) simultaneously. The device then

processes the sampled video signal with respect to the video reset level or the reference level VMID

using three processing channels.

Each processing channel consists of an input sampling block with optional reset level clamping

(RLC) and correlated double sampling (CDS), a 5-bit programmable gain amplifier (PGA) and an 8-

bit (+sign) programmable offset DAC.

For colour operation, the resulting analogue outputs from the three channels are multiplexed into a

12-bit ADC. For monochrome operation the resulting analogue output from the selected channel only

is multiplexed into the ADC. The ADC then converts the analogue signal to a 12-bit digital word. The

digital output from the ADC is presented on an 8-bit wide output bus, in 8+4-bit multiplexed format.

Internal control registers determine the configuration of the device, including the gain and offset

applied to each channel. These registers are programmable via the serial interface.

RESET LEVEL CLAMPING (RLC)

CONFIGURATION

To ensure that the signal applied to the WM8146 lies within its input range, the CCD output signal is

usually level shifted by a.c. coupling through a capacitor, CIN. The RLC circuit clamps the WM8146

side of this capacitor to a selected voltage during the CCD reset level. The RLC voltage VRLC, is

selected by control bits RLC[1:0] in setup register 3.

A typical input configuration demonstrating reset level clamping and CDS circuitry is shown in Figure

5. A clamp pulse, CL, is generated from MCLK and VSMP by the timing control block. When CL is

active the voltage on the WM8146 side of CIN, at RINP, is forced to the RLC voltage VRLC by switch

1. When the CL pulse turns off, the voltage at RINP initially remains at VRLC but any subsequent

variation in sensor voltage (from reset to video level) will couple through CIN to RINP.

Reset level clamping is compatible with both CDS and non-CDS operating modes, as selected by

switch 2.

RLC

MCLK VSMP

C IN

RINP

TIMING CONTROL

CL

RS

VS

2

1

RLC

S/H

S/H

CDS

VRLC

VRLC

AGND

VMID

FROM CONTROL

INTERFACE

+

+

TO PGA

-

INPUT SAMPLING

BLOCK FOR RED

CHANNEL

CDS FROM CONTROL

INTERFACE

Figure 5 Reset Level Clamping and CDS Circuitry

WOLFSON MICROELECTRONICS LTD

PP Rev 1.1 January 2000

7

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