WM8146 查看數據表（PDF） - Wolfson Microelectronics plc

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WM8146

12-bit (8+4-bit) Linear Sensor Image Processor

Wolfson Microelectronics plc 

WM8146

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TIMING

Figure 6 illustrates the use of the RLC pin, MCLK and VSMP to control the timing of the CL pulse for

a typical CCD waveform. The CL pulse is applied during the reset period.

The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during

each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal

CL pulse on the next reset level. The position of CL can be adjusted by using control bits

CDSREF[1:0], as shown in Figure 7.

The VRLC pin outputs the analogue RLC voltage selected via control set-up register 3 bits RLC[1:0].

MCLK

VSMP

RLC

1

X

X

Programmable Delay

CL

(CDSREF = 01)

0

X

X

0

INPUT VIDEO

RGB

RGB

RLC on this Pixel

RGB

No RLC on this Pixel

Figure 6 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL

CDS/NON-CDS PROCESSING

For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel

common mode noise. For CDS operation, the video level is processed with respect to the video reset

level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must

be set to 1 (default), this controls switch 2 (Figure 5) and causes the signal reference to come from

the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by

programming control bits CDSREF[1:0], as shown in Figure 7 .

For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed

with respect to the reference voltage VMID.

MCLK

VSMP

VS

RS/CL (CDSREF = 00)

RS/CL (CDSREF = 01)

RS/CL (CDSREF = 10)

RS/CL (CDSREF = 11)

Figure 7 Reset Sample and Clamp Timing

WOLFSON MICROELECTRONICS LTD

PP Rev 1.1 January 2000

8

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