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WM8146

12-bit (8+4-bit) Linear Sensor Image Processor

Wolfson Microelectronics plc 

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WM8146

OFFSET ADJUST AND PROGRAMMABLE GAIN

The output from the CDS block is a differential signal, which is amplified by a 5-bit PGA then added

to the output of an 8-bit (+sign) offset DAC to compensate for sensor d.c. offsets. The gain and offset

for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[4:0].

The following diagram shows the signal path through the device.

INPUT

SAMPLING

PGA OFFSET DAC

BLOCK

BLOCK

BLOCK

V1

V2

V3

V IN

+-

X

++

analog

CDS = 1

VRESET

CDS = 0

PGA gain

A = 0.5+(PGA[4:0]*0.25)

ADC BLOCK

V3 x (4096/VFS) +2047

OUTPUT

INVERT

BLOCK

D1

digital

TO MULTIPLEXER

FOR 8-BIT OUTPUT

D2

D2 = D1 if INVOP = 0

D2 =4095-D1 if INVOP = 1

V MID

Offset

DAC

VIN is RINP or GINP or BINP

(1-2*DSIGN)*(DAC[7:0]/255)*(V MID/2 + VMID/4*DACRNG)

VRESET is VIN sampled during reset clamp

VMID is AVDD/2

CDS, DAC[7:0], DSIGN, DACRNG, PGA[4:0]

and INVOP are set by programming internal

control registers.

CDS=1 for CDS, 0 for non-CDS

Figure 8 Signal Flow Diagram

The following equations enable the user to calculate the settings required for the PGAs and offset

DACs.

INPUT SAMPLING AND REFERENCING

If CDS=1, the previously sampled reset level, VRESET, is subtracted from the input video signal VIN

(i.e. CDS operation).

V1 = VIN - VRESET

If CDS=0, the simultaneously sampled VMID is subtracted instead (i.e. non-CDS operation).

V1 = VIN - VMID

GAIN ADJUST

The signal is then multiplied by the PGA gain, approximately 0.5 to 8.25 in 32 equal gain steps.

V2 = V1 * G

= V1 * (0.5+(PGA[4:0]*0.25))

OFFSET (BLACK-LEVEL) ADJUST

The resultant signal is added to the Offset DAC output which has a range of VMID/2 (or 1.5*VMID/2 if

the DACRNG bit is set).

V3 = V2 + VDAC

= V2 + [(1-2*DSIGN) * DAC_CODE/255 * (VMID/2 + VMID/4 * DACRNG)]

ANALOGUE TO DIGITAL CONVERSION

The analogue signal is then converted to a 12-bit unsigned number. This is equivalent to a

multiplication by 4096/(VFS), where VFS = 2V .

D1 == INT{ (V3/VFS) * 4096 } + 2047

At this stage, the input to the ADC should be between -1V and +1V, so D1[11:0] should lie between

-2047 and +2048. If the input is over-range, it will be clipped to within the range (-2047,2048).

2047 is added to the ADC output, to give code 2047 for zero input signal to the ADC. This is

equivalent to the +VMID shown in the block diagram on page 1.

WOLFSON MICROELECTRONICS LTD

PP Rev 1.1 January 2000

9

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