WM8192 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8192 Datasheet PDF : 24 Pages
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WM8192
INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
VSMP
INPUT
tVSMPSU
tVSMPH
tVSU
tVH
VIDEO
Product Preview
tRSU
tRH
Figure 1 Input Video Timing
Note:
1.
See Page 14 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated
PARAMETER
MCLK period
SYMBOL
tPER
TEST CONDITIONS
MIN
83.3
MCLK high period
tMCLKH
37.5
MCLK low period
tMCLKL
37.5
VSMP set-up time
tVSMPSU
10
VSMP hold time
tVSMPH
5
Video level set-up time
tVSU
15
Video level hold time
tVH
5
Reset level set-up time
tRSU
15
Reset level hold time
tRH
5
Notes:
1.
tVSU and tRSU denote the set-up time required after the input video signal has settled.
2.
Parameters are measured at 50% of the rising/falling edge.
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT DATA TIMING
MCLK
tPD
OP[7:0]
Figure 2 Output Data Timing
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 June 2000
6
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