Z801806FSC 查看數據表（PDF） - Zilog
零件编号
产品描述 (功能)
生产厂家
Z801806FSC Datasheet PDF : 85 Pages
| |||
Z80180
Microprocessor Unit
17
T1
T2
T3
T1
T2
T3
f
WR
M1
WRITE into OMCR
Opcode Fetch
Figure 10. M1 Temporary Enable Timing
IOC—This bit controls the timing of the IORQ and RD signals. It is set to 1 by RESET. When
IOC = 1, the IORQ and RD signals function the same as the Z64180 (Figure 11).
T1
φ
T2
TW
T3
IORQ
RD
WR
Figure 11. I/O READ and WRITE Cycles with IOC = 1
When IOC = 0, the timing of the IORQ and RD signals match the timing of the Z80. The
IORQ and RD signals go active as a result of the rising edge of T2 (see Figure 12).
T1
φ
IORQ
T2
TW
T3
RD
WR
Figure 12. I/O READ and WRITE Cycles with IOC = 0
PS014004-1106
Architecture
Share Link: 