Z801806FSC 查看數據表（PDF） - Zilog
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Z801806FSC Datasheet PDF : 85 Pages
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Table 8. Z80180-8 AC Characteristics (continued)
No Symbol Item
8 tMED1 Ø Fall to MREQ Fall Delay
9 tRDD1 Ø Fall to RD Fall Delay IOC = 1
Ø Rise to RD Rise Delay IOC = 0
10 tM1D1 Ø Rise to M1 Fall Delay
11 tAH
Address Hold Time from
(MREQ, IOREQ, RD, WR)
12 tMED2
13 tRDD2
14 tM1D2
15 tDRS
16 tDRH
17 tSTD1
18 tSTD2
19 tWS
20 tWH
21 tWDZ
22 tWRD1
23 tWDD
24 tWDS
25 tWRD2
26 tWRP
26a
Ø Fall to MREQ Rise Delay
Ø Fall to RD Rise Delay
Ø Rise to M1 Rise Delay
Data Read Set-up Time
Data Read Hold Time
Ø Fall to ST Fall Delay
Ø Fall to ST Rise Delay
WAIT Set-up Time to Ø Fall
WAIT Hold Time from Ø Fall
Ø Rise to Data Float Delay
Ø Rise to WR Fall Delay
Ø Fall to WRITE Data Delay Time
WRITE Data Set-up Time to WR Fall
Ø Fall to WR Rise Delay
WR Pulse Width
WR Pulse Width (I/O WRITE Cycle)
27 tWDH
28 tIOD1
WRITE Data Hold Time from (WR Rise)
Ø Fall to IORQ Fall Delay IOC = 1
Ø Rise to IORQ Fall Delay IOC = 1
29 tIOD2
30 tIOD3
31 tINTS
Ø Fall to IORQ Rise Delay
M1 Fall to IORQ Fall Delay
INT Set-up Time to Ø Fall
PS014004-1106
Z80180
Microprocessor Unit
25
Z80180-8
Min Max Unit
–
50 ns
–
50 ns
–
60
–
70 ns
20 –
ns
–
50 ns
–
50 ns
–
70* ns
30 –
ns
0
–
ns
–
70 ns
–
70 ns
40 –
ns
40 –
ns
–
70 ns
–
60 ns
–
80 ns
20 –
ns
–
60 ns
130 –
ns
255 –
ns
15 –
–
50 ns
–
60
–
50 ns
250 –
ns
40 –
ns
Architecture
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