Z8917520ASC 查看數據表（PDF） - Zilog

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Z8917520ASC

VOICE PROCESSING CONTROLLERS

Zilog 

Zilog

PIN DESCRIPTION

P00

P01

P02

Address P03

or I/O

(Nibble

Programmable)

P04

P05

P06

P07

P10

P11

P12

Address/Data

or I/O

P13

(Byte

P14

Programmable) P15

P16

P17

P20

P21

I/O

(Bit

P22

P23

Programmable) P24

P25

P26

P27

Port 0

Port 1

Port 2

RMLS

/AS

/DS

R/W

XTAL1

XTAL2

VDD

GND

/RESET

OSC1

OSC2

Ext.

Memory

Control

OSC

Power

32 kHz

OSC

Z89175/Z89176

Voice Processing Controllers

Timer 0

Capture Reg.

Timer 1

Register File

256 x 8 Bit

Register Bus

24 Kbytes

Program

ROM

(Z89175)

Internal Address Bus

Internal Data Bus

Expanded Register

File

(Z8)

Z8 Core

Expanded

Register Bus

Port 3

Port 4

Peripheral

Register

(DSP)

mailbox

Extended Bus of the DSP

256 Word 256 Word

RAM 0

RAM 1

8K Words

Program

ROM

Timer 2

Internal Address Bus

Internal Data Bus

INT 1

INT 2

DSP Core

Timer 3

Extended Bus of the DSP

Port 5

DSP Port

PWM

(10-Bit)

ADC

(8-Bit)

2

P31

P32 Input

P33

P34

P35 Output

P36

P37

P40

P41

P42

I/O

P43

(Bit

P44 Programmable)

P45

P46

P47

P50

P51

P52

I/O

P53

(Bit

P54 Programmable)

P55

P56

P57

DSP0

DSP1

PWM

AN IN

AN VDD

AN GND

VREF+

VREF-

Figure 1. Z89175/176 Functional Block Diagram

DS97TAD0100

PRELIMINARY

3

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