Z80189 查看數據表（PDF） - Zilog

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Z80189

GENERAL-PURPOSE EMBEDDED CONTROLLERS

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PRELIMINARY

System Control Signals (Continued)

Z80189/Z8L189

GENERAL-PURPOSE EMBEDDED CONTROLLERS

/IOCS2. I/O Chip Select 2 (output, active Low) This pin is

a secondary peripheral I/O chip select. This pin is active for

I/O accesses between XXC0H to XXC7H or XXC8H to

XXCFH (programmable by bit 1 of the IOBRG register).

/RAMCS. RAM Chip Select (Output, active Low). Signal

used to access RAM based upon the address and the

RAMLBR and RAMUBR registers.

/ROMCS. ROM Chip Select (Output, active Low). Signal

used to access ROM based upon the address and the

ROMBR register.

XTAL. Crystal (Output, active High). Crystal oscillator

connection. This pin should be left open if an external clock

is used instead of a crystal. The oscillator input is not a TTL

level (reference DC characteristics).

EXTAL. External Clock/Crystal (Input, active High). Crystal

oscillator connections. An external clock can be input to

the Z80189 on this pin when a crystal is not used. This input

is Schmitt-triggered.

PHI. System Clock (Output, active High). The output is

used as a reference clock of the MPU and the external

system.

V . Power Supply. +5 Volts

CC

VSS. Power Supply. 0 Volts

PIN MULTIPLEXING

To allow for COM Port decode and omission of ESCC core,

Pin Multiplexing is changed with respect to the Z182.

ESCC CH.A pins will be replaced by COM Decode and

ASCI CH.A pins as follows:

RxDA

→

/TRxCA →

TxDA

→

DCDB

→

/CTSB

→

HA6

HAEN

HINTR2

/HRD//DCD0

/HWR//CTS0

Note that ASCI channel 0 functions can be found in two

places. These pins are ORed with ASCI channel 0 func-

tions that are multiplexed with Port B (pins 35-39 QFP).

/DCD0, /CTS0, RXA0 inputs will come from 78, 79, 81

(respectively) when Port B (0-4) is enabled. When MIMIC

is disabled, /HDDIS pin doubles as TXA0 output. Note that

/RTS0 has also been changed to pin 50.

When COM decode bit is set (enabled during reset) the

following pins become multiplexed as follows.

/RFSH

→

/WAIT

→

/DREQ1

→

/HA6

→

IEI

→

/HA8

→

CKA1/TEND0 →

/HAEN

→

HA3

HA4

HA5

HA6

HA7

HA8

HA9

HAEN

These pins are selected such that they are all high-z inputs

at power up to prevent any problems with connecting

address lines directly to PC bus. Although, the COM

decode multiplexing is enabled on power-up, the COM

address decoding is disabled.

30

DS971890301

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