MSM6255GS-K 查看數據表（PDF） - Oki Electric Industry
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MSM6255GS-K Datasheet PDF : 39 Pages
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¡ Semiconductor
MSM6255
PIN DESCRIPTIONS
Pin Symbol
1-6
MA0
71 - 80
7
MA15
A0
22
A15
23
FRP
24
LIP
25
CEφ
26
CLP
27
FRMB
28
LD0
31
LD3
32
VDD
33
UD0
36
UD3
37
CHφ
38
Busy
39
DIEN
40
ADF
41
CS
42
RD
43
WR
44
RES
45
DB0
52
DB7
53
RD0
60
RD7
61
RA0
64
RA3
65
XT
66
XT
67
VSS
70
DIV
Type
O
I
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I/O
I
O
I
O
—
I
Description
Address output for displaying RAM.
MA0 - MA15 are high impedance when ADF = "L".
Memory address input pins
Frame signal. Synchronization of display
Display data latch signal
Chip enable clock for LCD segment driver
Display data shift clock
Alternate signal output pin
Display data parallel output for lower side
Supply voltage
Display data parallel output, Upper display 4-bit output
(OD1, ED1, OD2 and ED2 outputs)
Character clock
Ready state signal. This signal is used while serial transmission stops.
Display enable signal. When this signal is "H", display is enabled.
Address floating input. When this signal is "L", MA0 - MA15, RA0 - RA3 are high impedance,
and when it is "H", A0 - A15 or a refresh address is output to MA0 - MA15.
Chip select. CS = "L"
Read. Reading data is valid when RD = "L"
Write. Data is written when WR = "H"
Reset. Resets each counter.
8-bit data bus. Common pins for 3-state I/O.
ROM/RAM data input. Dot pattern data for the character generator
Raster address output.
*This output is not used in the graphic mode.
RA0 - RA3 are high impedance when ADF = "L".
X’tal osc. When an external clock is used by setting DIV to "H", feeds it to XT.
Ground pin.
"H" : EXT clock
"L" : Self oscillation
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