MSM6255GS-K 查看數據表（PDF） - Oki Electric Industry

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MSM6255GS-K

DOT MATRIX LCD CONTROLLER

Oki Electric Industry 

¡ Semiconductor

MSM6255

TIMING DIAGRAM

LCDC Control Signal Timing Characteristics

Parameter

Clock Cycle Time

Clock "H" Level Pulse Width

Clock "L" Level Pulse Width

Clock Rise/Fall Time

Character Clock Delay Time

Memory Address Clock Delay Time

Memory Address Disable Delay Time

Memory Address Enable Delay Time

CPU Address Delay Time

Refresh Address Delay Time

Reset "H" Level Pulse Width

CPU Address Delay Time

Symbol

tCP

PWH

PWL

tcr/tcf

tCH

tMA

tAD1

tAD2

tAD3

tAD4

tRES

tAD5

(CL = 30pF, VDD = 5V ± 5%, Ta = –20 to +85°C)

Min.

Typ.

Max.

Unit

180

—

—

ns

80

—

—

ns

80

—

—

ns

—

—

20

ns

—

—

200

ns

—

—

100

ns

—

—

40

ns

—

—

40

ns

—

—

100

ns

—

—

100

ns

1

—

—

ms

—

—

100

ns

XT

(External clock)

CHφ

tCP

PWL

PWH

tcr

tcf

tCH

MA0 - MA15

Upper Side Address

tMA

ADF

Lower Side Address

tMA

MA0 - MA15

RA0 - RA3

DIEN

VALID

tAD1

Floating

VALID

tAD2

MA0 - MA15

RES

A0 - A15

MA0 - MA15

Refresh Address

CPU Address

tAD3

tRES

tAD5

Refresh Address

tAD4

tAD5

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