MAX7490EEE(2000) 查看數據表（PDF） - Maxim Integrated

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MAX7490EEE
(Rev.:2000)

Dual Universal Switched-Capacitor Filters

Maxim Integrated 

Dual Universal Switched-Capacitor Filters

PIN

LP_

BP_

N_/HP_

INV_

S_

SHDN

GND

VDD

CLK

EXTCLK

COM

NAME

FILTER A

FILTER B

1

16

2

15

3

14

4

13

5

12

6

7

8

9

10

11

Pin Description

FUNCTION

2nd-Order Lowpass Filter Output

2nd-Order Bandpass Filter Output

2nd-Order Notch/Highpass Filter Output

Inverting Input of Filter Summing Op Amp

Summing Input. The connection of the summing input, along with the other

resistor connections, determine the circuit topology (mode) of each 2nd-

order section. S_ must never be left floating.

Shutdown Input. Drive SHDN low to enable shutdown mode; drive high or

connect to VDD for normal operation.

Ground Pin

Positive Supply. VDD should be bypassed with a 0.1µF capacitor to GND. A

low-noise supply is recommended. Input +5V for MAX7490 or +3V for

MAX7491.

Clock Input. Connect to an external capacitor (COSC) between CLK and

ground to set the internal oscillator frequency. For external clock operation,

drive with a CMOS-level clock. The duty cycle of the external clock should be

between 45% and 55% for best performance.

External/Internal Clock Select Input. Connect EXTCLK to VDD when driving

CLK externally. Connect to GND when using the internal oscillator.

Common Pin. Biased internally at VDD/2. Bypass externally to GND with

0.1µF capacitor. To override the internal biasing, drive with an external low-

impedance source.

_______________Detailed Description

The MAX7490/MAX7491 are universal switched-capaci-

tor filters designed with a fixed internal fCLK/fO ratio of

100:1. Operating modes use external resistors connect-

ed in different arrangements to realize different filter

functions (highpass, lowpass, bandpass, notch) in all of

the classical filter topologies (Butterworth, Bessel, ellip-

tic, Chebyshev). Figure 1 shows a block diagram.

Clock Signal

External Clock

The MAX7490/MAX7491 switched-capacitor filters are

designed for use with external clocks that have a 50%

±5% duty cycle. When using an external clock, drive

the EXTCLK pin high or connect to VDD. Drive CLK with

CMOS logic levels (GND and VDD). Varying the rate of

the external clock adjusts the center frequency of the

filter:

fO = fCLK /100

Internal Clock

When using the internal oscillator, drive the EXTCLK pin

low or connect to GND and connect a capacitor (COSC)

between CLK and GND. The value of the capacitor

(COSC) determines the oscillator frequency as follows:

fOSC (kHz) = 135 x 103 / COSC (pF)

Since COSC is in the low picofarads, minimize the stray

capacitance at CLK so that it does not affect the inter-

nal oscillator frequency. Varying the frequency of the

internal oscillator adjusts the filter’s center frequency by

a 100:1 clock-to-center frequency ratio. For example,

an internal oscillator frequency of 135kHz produces a

nominal center frequency of 1.35kHz.

8 _______________________________________________________________________________________

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