STM6503SFABDG6F 查看數據表（PDF） - STMicroelectronics

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STM6503SFABDG6F

Dual push-button Smart Reset™ with user-adjustable setup delays

STMicroelectronics 

DC and AC parameters

STM6502, STM6503, STM6504, STM6505

Table 6.

Symbol

DC and AC characteristics (continued)

Parameter

Test conditions(1)

Min. Typ.(2) Max. Unit

Smart Reset inputs

VIL

VIH

ILI(SR)

SR0, SR1, SRE input

voltage low

SR0, SR1, SRE input

voltage high

Input leakage current, SR

and SRE inputs

Option without internal pull-up resistor

VSS

–0.3

0.7

VCC

–1

0.3

VCC

V

5.5 V

+1 µA

ILI(TSR)

Input leakage current, TSR

input

STM6503 and STM6504 only

–5

+7 µA

RPUI

Internal pull-up resistor,

input (optional - refer to

Table 12)

65

kΩ

tDEBOUNCE

SRE input falling edge

debounce time

STM6504 only

240 360 480 ms

Smart Reset delay

tSRC(5)

Capacitor-programmable

Smart Reset setup time,

STM6502 and STM6505.

Refer to Table 3.

TA = 25 °C

10 x 12.5 x 15 x

CSRC CSRC CSRC s

(µF) (µF) (µF)

tSRC(5)

TSR pin-programmable

Smart Reset setup time,

STM6503 and STM6504.

TSR = VSS

TSR = floating(6)

TSR = VCC

2

2.5

3

s

6

7.5

9

s

10 12.5 15 s

1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 to 5.5 V (except where noted).

2. Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted.

3. For devices with VRST < 3.0 V.

4. Guaranteed by design.

5. Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite). STM6502, STM6503, STM6505

only.

6. If left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic

capacitor between the TSR and VSS pins.

18/29

Doc ID 16101 Rev 6

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