MC145073DW 查看數據表（PDF） - Motorola => Freescale

零件编号

产品描述 (功能)

生产厂家

MC145073DW

Dual 16-Bit Stereo Audio Sigma-Delta ADC

Motorola => Freescale 

IJUST

Serial Interface Data Justification Select Input (Pin 16)

A low level on the IJUST pin will cause the serial output data

to be left justified relative to the SYNC signal. A high level on

the IJUST pin will select right justification of the serial output

data. See the Summary of Operating Modes and the Serial

Interface Description sections for more information.

IDOE

Serial Interface Data Output Enable (Pin 15)

This pin controls the state of the SDO pin between 16–bit

data word transfers. A high level on this pin will force the

SDO pin to a low level between serial data words, while a low

level on the IDOE pin will force the SDO pin to a high–imped-

ance state between data words. See the Summary of Oper-

ating Modes and the Serial Interface Description sections

for more information.

POWER SUPPLY PINS

VDD(A) (Pin 4)

Positive analog power supply input. The voltage range for

this pin is 4.5 to 5.5 V with respect to VSS(A). The absolute

value of the difference between VDD(A) and VDD(D) must not

exceed 0.5 V. For proper device operation, this pin should be

decoupled to VSS(A) with a 1.0 µF or larger capacitor.

VSS(A) (Pin 5)

Negative analog power supply input. This pin should be

connected to ground for normal device operation.

VDD(D) (Pin 8)

Positive digital power supply input. The voltage range for

this pin is 4.5 to 5.5 V with respect to VSS(D). The absolute

value of the difference between VDD(A) and VDD(D) must not

exceed 0.5 V. For proper device operation, this pin should be

decoupled to VSS(D) with a 1.0 µF or larger capacitor.

VSS(D) (Pin 7)

Negative digital power supply input. This pin should be

connected to ground for normal device operation.

SUB (Pin 6)

Substrate connection. This pin should be connected to

VSS(A) for normal device operation.

FUNCTIONAL DESCRIPTION

The MC145073 is a 16–bit stereo audio A/D converter in-

tended for use in digital audio systems. The MC145073 uses

a sigma–delta architecture consisting of a second order ana-

log modulator followed by two stages of digital filtering for

each channel. The analog modulator samples the input sig-

nal at a very high rate (128x the output data rate), performs a

single bit quantization, and shapes the quantization noise to-

wards out–of–band frequencies. The digital filters of the

MC145073 reject most of the shaped quantization noise, and

lower the serial data output rate. The digital filtering is imple-

mented with a 5th order, decimate–by–32 comb filter followed

by a 121 tap, decimate–by–4, FIR filter on each channel. In

addition to rejecting quantization noise, the FIR filter cancels

the curvature in the response of the preceding comb filter.

The comb and FIR filters also provide anti–alias filtering of

out–of–band signals present at the input to the device. The

analog inputs to the MC145073 can be fully differential (both

inputs dynamic and 180 degrees out of phase), or single–en-

ded (positive inputs dynamic while negative inputs are static

at a level in the middle of the supply range). Analog input sig-

nals that exceed the differential analog input voltage range of

3.8 V p–p are clipped in order to prevent overflow of the digi-

tal filters. The MC145073 operates from a single 5 V power

supply. For portable or other low power applications, a pow-

er–down mode is available.

The operation of the MC145073 can be tailored to specific

applications by proper selection of the states of seven mode

select pins. These mode pins control the divide ratio of the

master clock, the FIR filter response, and the serial interface

format. The master clock input can be divided by either 1, 2,

or 3 to yield the input sampling rate. This means that the in-

put clock frequency is either 128x, 256x, or 512x the serial

output data rate.

NOTE

The oversampling ratio (OSR), which is the

ratio of input sampling frequency to output data

rate, is 128x in all three cases.

Two sets of FIR filter coefficients are stored in the on–

board ROM of the MC145073. One set provides a transition

band from 20 kHz to 25.8 kHz for operation at the 48 kHz out-

put data rate. The other set of FIR filter coefficients provides

a transition band from 20 kHz to 25 kHz for use with the

44.1 kHz output data rate.

Four mode select pins configure the serial interface. This

yields sixteen possible serial interface operating modes.

Included are modes that provide for interfacing directly to

Motorola and TI general purpose DSPs, multiplexing of two

MC145073s, as well as formats similar to the CS5326 inter-

face.

MC145073

10

MOTOROLA

Share Link: