MC145073DW 查看數據表（PDF） - Motorola => Freescale
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MC145073DW Datasheet PDF : 16 Pages
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SUMMARY OF DEVICE OPERATING MODES
The seven pins summarized in the tables below configure
the MC145073 to operate in one of the modes specified. The
modes can be chosen in any combination.
CSEL1
0
0
1
1
CSEL0
0
1
0
1
Master CLK Divider Select
Power–Down
Divide CLK by 1
Divide CLK by 2
Divide CLK by 3
FSEL
0
1
FIR Filter Transition Band Select
20 kHz – 25.8 kHz Transistion Band
6.144 MHz Input Rate, 48 kHz Output Data Rate.
20 kHz – 25 kHz Transistion Band
5.6448 MHz Input Rate,
44.1 kHz Output Data Rate
ISYNC
0
1
Serial Interface SYNC Signal Format
SYNC rising edge is one SCLK cycle before the
start of the serial output data transfer. (This is
compatible with the DSP5600/56001 and TMS320
interface definitions.)
SYNC rising edge is coincident with the start of the
serial output data transfer. (This is compatible with
the CS5326 interface definition.)
ISLAV
0
1
Serial Interface Master or Slave Select
MC145073 is a master, SYNC and SCLK are
outputs.
MC145073 is a slave, SYNC and SCLK are inputs
(re–clocked by the MC145073 internal clock, CLKI).
IJUST
0
1
Serial Interface Data Justification Select
Serial output data is left justified relative to the
SYNC signal.
Serial output data is right justified relative to the
SYNC signal.
IDOE
0
1
Serial Interface Data Output Enable
SDO goes to a high–impedance state between
16–bit output words.
SDO is forced low between 16–bit output words.
SERIAL INTERFACE DESCRIPTION
As summarized in the previous section, the format of the
serial interface is controlled by four mode pins: ISYNC, ISLAV,
IJUST, and IDOE. These control inputs can be configured in
any combination, yielding 24 = 16 unique modes. The follow-
ing two subsections describe the format of the serial inter-
face for these various modes. Timing information for the
serial interface is provided in the AC Electrical Specifica-
tions section .
Compatibility with the DSP56000/1 and TMS320 general–
purpose DSPs is accomplished by applying the appropriate
logic level to the ISYNC pin. The phase of the rising edge of
the SYNC signal is different for the DSP56000 and TMS320
applications, while the falling edge of SYNC is not critical in
such applications.
To interface to one or two MC145073s, the
DSP56000/56001 should be configured as follows: network
mode, four time slots per frame, 16 bits per slot, continuous
clock, and control signals configured as either a master or
slave. If interfacing to a TMS320 is desired, the serial inter-
face should be configured in continuous mode without frame
sync.
NOTE
The TMS320 interface must be initialized with
frame sync enabled, and then switched to the no
frame sync mode after initialization.
The IJUST and IDOE serial interface mode control inputs
are provided to facilitate multiplexing of two MC145073s.
The IJUST input selects between left and right justification of
the serial output data relative to the SYNC signal, while the
IDOE input provides a way to force the SDO pin to the high
impedance state between the output data words. To multi-
plex the serial data outputs of two MC145073s onto the
same SDO line, IDOE must be forced low on both
MC145073s, while the IJUST pin is forced high on one
MC145073 and low on the other. The MC145073s must be in
the slave mode (ISLAV=1) when multiplexing. It is not pos-
sible to operate with one MC145073 as a master tied to a
second MC145073 operating as a slave due to the reclock-
ing of the SYNC and SCLK inputs in the slave mode (see
Operation with the MC145073 as a Slave (ISLAV = 1) sec-
tion).
NOTE
When multiplexing two MC145073 devices, all
four analog channels are sampled at exactly the
same phase.
In Figures 10 and 11, the internal clock signal CLKI is
plotted instead of CLK. This is due to the fact that all internal
clocks, as well as the serial interface, are slaved to this
divided version of the master clock. Input signals to the serial
interface are reclocked by CLKI to reduce the amount of
noise injected into the analog section of the MC145073. Seri-
al output data and high–impedance states of the SDO pin are
clocked out relative to CLKI. This reclocking can cause a
shift in phase of SDO relative to SCLK when operating in the
slave mode. In cases where the MC145073 output is multi-
plexed with another device, the clock divide by 1 mode is
recommended.
NOTE
If the clock divide by 2 or 3 mode is selected, it
is impossible to know the exact phase of CLKI.
On initial power–up or recovery from a power–down condi-
tion, the first 68 serial output words of the MC145073 are
indeterminate. This is because the digital filters and internal
logic of the MC145073 must settle. This time is also used to
charge the external REF filter capacitor.
MOTOROLA
MC145073
11
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