LTC2451 查看數據表（PDF） - Linear Technology

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LTC2451

Ultra-Tiny, 16-Bit DS ADC with I2C Interface

Linear Technology 

LTC2451

APPLICATIONS INFORMATION

The user can send one byte of data into the LTC2451

following a Write request and an ACK. The sequence is

shown in Figure 3. The Write sequence is used solely to

set the conversion speed. The default conversion speed

is 60Hz. The user can specify a 30Hz conversion speed by

setting the eighth bit (S30) = 1, or specify a 60Hz conversion

speed by setting the eighth bit (S30) = 0.

After a Read request and an ACK, the LTC2451 can output

data, as shown in Figure 4. The data output stream is 16 bits

long and is shifted out on the falling edges of SCL. The first

bit is the MSB (D15) and is followed by successively less

significant bits (D14, D13 ...) until the LSB (D0) is output by

the LTC2451. This sequence is summarized in Figure 5.

OPERATION SEQUENCE

Continuous Read

Conversions from the LTC2451 can be continuously read

(see Figure 7). At the end of a Read operation, a new

conversion automatically begins. At the conclusion of

the conversion cycle, the next result may be read using

the method described above. If the conversion cycle is

not concluded and a valid address selects the device, the

LTC2451 generates a NAK signal indicating the conversion

cycle is in progress.

1

7

8 91

2

3

4

5

6

78

9

SCL

SDA

7-BIT

ADDRESS

W

S30 = 1: 30Hz MODE

S30 S30 = 0: 60Hz MODE

START BY

MASTER

SLEEP

ACK BY

LTC2451

DATA INPUT

Figure 3. Timing Diagram for Write Sequence

ACK BY

MASTER

2451 F03

1

7

8

9

1

2

3

8

9

1

2

3

89

SCL

7-BIT

SDA

ADDRESS

START BY

MASTER

SLEEP

R

D15 D14 D13

MSB

ACK BY

LTC2451

D8

D7 D6 D5

ACK BY

MASTER

DATA OUTPUT

Figure 4. Timing Diagram for Read Sequence

D0

LSB

NACK BY

MASTER

CONVERT

2451 F04

10

CONVERSION

7-BIT ADDRESS

S

(0010100)

R ACK

READ

P

SLEEP

DATA OUTPUT

Figure 5. Conversion Sequence

CONVERSION

2451 F05

2451ff

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