74VHC139SJX 查看數據表（PDF） - Fairchild Semiconductor

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74VHC139SJX

Dual 2-to-4 Decoder/Demultiplexer

Fairchild Semiconductor 

Logic Symbols

IEEE/IEC

Functional Description

The VHC139 is a high-speed dual 2-to-4 decoder/demulti-

plexer. The device has two independent decoders, each of

which accepts two binary weighted inputs (A0–A1) and pro-

vides four mutually exclusive active-LOW outputs (O0–O3).

Each decoder has an active-LOW enable (E). When E is

HIGH all outputs are forced HIGH. The enable can be used

as the data input for a 4-output demultiplexer application.

Each half of the VHC139 generates all four minterms of

two variables. These four minterms are useful in some

applications, replacing multiple gate functions as shown in

Figure 1, and thereby reducing the number of packages

required in a logic network.

Logic Diagram

FIGURE 1. Gate Functions (Each Half)

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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