SN74LS256D 查看數據表（PDF） - Motorola => Freescale
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SN74LS256D Datasheet PDF : 6 Pages
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SN54 / 74LS256
AC SET-UP REQUIREMENTS (TA = 25°C)
Symbol
ts
ts
th
th
tW
Parameter
Data Setup Time
Address Setup Time
Data Hold Time
Address Hold Time
Enable Pulse Width
Limits
Min Typ Max Unit
20
ns
0
ns
0
ns
15
ns
15
ns
Test Conditions
Figures 4 & 6
Figure 4
Figure 6
Figure 1
VCC = 5.0 V
AC WAVEFORMS
D
tpw
E
tPHL
Q
tpw
1.3 V
tPLH
1.3 V
OTHER CONDITIONS: CL = H, A = STABLE
Figure 1. Turn-on and Turn-off Delays, Enable To
Output and Enable Pulse Width
D
1.3 V
1.3 V
tPHL
tPLH
Q
1.3 V
1.3 V
OTHER CONDITIONS: E = L, CL = H, A = STABLE
Figure 2. Turn-on and Turn-off Delays,
Data to Output
A1
1.3 V
1.3 V
A1
Q1
1.3 V
tPHL
1.3 V
1.3 V
tPLH
1.3 V
OTHER CONDITIONS: E = L, CL = L, D = H
Figure 3. Turn-on and Turn-off Delays,
Address to Output
D
th(H)
th(L)
ts(H)
E
ts(L)
1.3 V
Q=D
Q
Q=D
OTHER CONDITIONS: C = H, A = STABLE
Figure 4. Setup and Hold Time, Data to Enable
C
1.3 V
tPHL
1.3 V
Q
OTHER CONDITIONS: E = H
Figure 5. Turn-on Delay, Clear to Output
A
1.3 V STABLE ADDRESS
ts
th
E
1.3 V
OTHER CONDITIONS: CL = H
Figure 6. Setup Time, Address to Enable
(See Notes 1 and 2)
NOTES:
1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
addressed and the other latches are not affected.
2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.
FAST AND LS TTL DATA
5-424
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