MX29LV320E 查看數據表（PDF） - Macronix International

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MX29LV320E

32M-BIT [4M x 8 / 2M x 16] 3V SUPPLY FLASH MEMORY

Macronix International 

MX29LV320E T/B

Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORM........................................................................... 45

Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM...................................................................... 45

Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM.................................................................... 46

Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART..................................................... 47

SECTOR GROUP PROTECT/CHIP UNPROTECT............................................................................................... 48

Figure 13. SECTOR GROUP PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)................ 48

Figure 14. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv............................................... 49

Figure 15. CHIP UNPROTECT ALGORITHM WITH RESET#=Vhv............................................................. 50

Table 5. TEMPORARY SECTOR GROUP UNPROTECT............................................................................ 51

Figure 16. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORM.................................................. 51

Figure 17. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART................................................ 52

Figure 18. SILICON ID READ TIMING WAVEFORM................................................................................... 53

WRITE OPERATION STATUS............................................................................................................................... 54

Figure 19. DATA# POLLING TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)........................ 54

Figure 20. DATA# POLLING ALGORITHM.................................................................................................. 55

Figure 21. TOGGLE BIT TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)............................. 56

Figure 22. TOGGLE BIT ALGORITHM........................................................................................................ 57

Figure 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to

word mode).................................................................................................................................................. 58

RECOMMENDED OPERATING CONDITIONS..................................................................................................... 59

ERASE AND PROGRAMMING PERFORMANCE................................................................................................ 60

DATA RETENTION................................................................................................................................................ 60

LATCH-UP CHARACTERISTICS.......................................................................................................................... 60

TSOP PIN CAPACITANCE.................................................................................................................................... 60

ORDERING INFORMATION.................................................................................................................................. 61

PART NAME DESCRIPTION................................................................................................................................. 62

PACKAGE INFORMATION.................................................................................................................................... 63

REVISION HISTORY ............................................................................................................................................. 67

P/N:PM1575

REV. 1.3, DEC. 19, 2013

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