DM93L28 查看數據表（PDF） - Fairchild Semiconductor
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DM93L28 Datasheet PDF : 5 Pages
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Functional Description
The two 8-bit shift registers have a common clock input
(pin 9) and separate clock inputs (pins 10 and 7). The
clocking of each register is controlled by the OR function of
the separate and the common clock input. Each register is
composed of eight clocked RS master/slave flip-flops and a
number of gates. The clock OR gate drives the eight clock
inputs of the flip-flops in parallel. When the two clock inputs
(the separate and the common) to the OR gate are LOW,
the slave latches are steady, but data can enter the master
latches via the R and S input. During the first LOW-to-
HIGH transition of either, or both simultaneously, of the two
clock inputs, the data inputs (R and S) are inhibited so that
a later change in input data will not affect the master; then
the now trapped information in the master is transferred to
the slave. When the transfer is complete, both the master
and the slave are steady as long as either or both clock
inputs remain HIGH. During the HIGH-to-LOW transition of
the last remaining HIGH clock input, the transfer path from
master to slave is inhibited first, leaving the slave steady in
its present state. The data inputs (R and S) are enabled so
that new data can enter the master. Either of the clock
inputs can be used as clock inhibit inputs by applying a
logic HIGH signal. Each 8-bit shift register has a 2-input
multiplexer in front of the serial data input. The two data
inputs D0 and D1 are controlled by the data select input (S)
following the Boolean expression:
Serial data in: SD = SD0 + SD1
An asynchronous master reset is provided which, when
activated by a LOW logic level, will clear all 16 stages inde-
pendently of any other input signal.
Shift Select Table
Inputs
S
D0
D1
L
L
X
L
H
X
H
X
L
H
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
n+8 = Indicates state after eight clock pulse
Output
Q7 (tn+8)
L
H
L
H
Logic Diagram
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