MCP6N16-010E/MF 查看數據表（PDF） - Microchip Technology

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MCP6N16-010E/MF

Zero-Drift Instrumentation Amplifier

Microchip Technology 

MCP6N16

3.0 PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP6N16

MSOP DFN

Symbol

Description

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

—

9

EN

VIM

VIP

VSS

VREF

VFG

VOUT

VDD

EP

Enable Input

Inverting Input

Non-inverting Input

Negative Power Supply

Reference Input

Feedback Input

Output

Positive Power Supply

Exposed Thermal Pad (EP); must be connected to VSS.

3.1 Digital Enable Input (EN)

This input (EN) is a CMOS, Schmitt-triggered input.

When it is low, it puts the part in a low-power state.

When high, the part operates normally. The EN pin

must not be left floating.

3.5 Analog Feedback Input (VFG)

The analog feedback input (VFG) is the inverting input

of the second input stage. The external feedback

components (RF and RG) are connected to this pin. It is

a high-impedance CMOS input with low bias current.

3.2 Analog Signal Inputs (VIP, VIM)

The non-inverting and inverting inputs (VIP and VIM) are

high-impedance CMOS inputs with low bias currents.

3.3 Power Supply Pins (VSS, VDD)

The positive power supply (VDD) is 1.8V to 5.5V higher

than the negative power supply (VSS). For normal

operation, the other pins are between VSS and VDD.

Typically, these parts are used in a single (positive)

supply configuration. In this case, VSS is connected to

ground and VDD is connected to the supply; VDD will

need bypass capacitors.

3.4 Analog Reference Input (VREF)

The analog reference input (VREF) is the non-inverting

input of the second input stage; it shifts VOUT to its

desired range. The external gain resistor (RG) is

connected to this pin. It is a high-impedance CMOS

input with low bias current.

3.6 Analog Output (VOUT)

The analog output (VOUT) is a low impedance voltage

output. It represents the differential input voltage

(VDM = VIP – VIM), with gain GDM and is shifted by

VREF. The external feedback resistor (RF) is connected

to this pin.

3.7 Exposed Thermal Pad (EP)

There is an internal connection between the exposed

thermal pad (EP) and the VSS pin; they must be

connected to the same potential on the printed circuit

board (PCB).

This pad can be connected to a PCB ground (VSS)

plane region to provide a larger heat sink. This

improves the package thermal resistance (θJA).

DS20005318A-page 36

 2014 Microchip Technology Inc.

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