MCP6N16-010E/MF 查看數據表（PDF） - Microchip Technology

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MCP6N16-010E/MF

Zero-Drift Instrumentation Amplifier

Microchip Technology 

4.0 APPLICATIONS

The MCP6N16 instrumentation amplifier (INA) is

manufactured using Microchip’s state of the art CMOS

process. Its low cost, low power and high speed make

it ideal for battery-powered applications.

4.1 Basic Performance

4.1.1 STANDARD CIRCUIT

Figure 4-1 shows the standard circuit configuration for

these INAs. When the inputs and output are in their

specified ranges, the output voltage is approximately:

EQUATION 4-1:

VOUT  VREF + GDMVDM

Where:

GDM = 1 + RF / RG

VDD U1

VIP

MCP6N16

VOUT

VIM

VFG

RF

RG

VREF

FIGURE 4-1:

Standard Circuit.

For normal operation, keep:

• VIP, VIM, VREF and VFG between VIVL and VIVH

• VIP – VIM (i.e., VDM) between VDML and VDMH

• VOUT between VOL and VOH

4.1.2 ANALOG ARCHITECTURE

Figure 4-2 shows the block diagram for these INAs,

without details on chopper-stabilized operation.

VDD VSS EN

I4

VIP VIP GM1

RM4 VOUT

GM2 VFG

VOUT

RF

VIM VIM

I1 Σ I2

MCP6N16

VREF

RG

RR VREF

FIGURE 4-2:

MCP6N16 Block Diagram.

The input signal is applied to GM1. Equation 4-2 shows

the relationships between the input voltages (VIP and

VIM) and the common mode and differential voltages

(VCM and VDM).

 2014 Microchip Technology Inc.

MCP6N16

EQUATION 4-2:

VIP = VCM + VDM  2

VIM = VCM – VDM  2

VCM = VIP + VIM  2

VDM = VIP – VIM

The negative feedback loop includes GM2, RM4, RF and

RG. These blocks set the DC open-loop gain (AOL) and

the nominal differential gain (GDM):

EQUATION 4-3:

AOL = GM2RM4

GDM = 1 + RF  RG

AOL is very high, so I4 is very small and I1 + I2 ≈ 0. This

makes the differential inputs to GM1 and GM2 equal in

magnitude and opposite in polarity. Ideally, this gives:

EQUATION 4-4:

VFG – VREF = VDM

VOUT = VDMGDM + VREF

For an ideal part, changing VCM, VSS or VDD produces

no change in VOUT. VREF shifts VOUT as needed.

The different GMIN options change GM1, GM2 and the

internal compensation capacitor. This results in the

performance trade-offs shown in Table 1.

4.1.3 DC ERRORS

Section 1.5 “Explanation of DC Error

Specifications” defines some of the DC error

specifications. These errors are internal to the INA, and

can be summarized as follows:

EQUATION 4-5:

VOUT = VREF + GDM1 + gEVDM + VED

Where:

+ GDM1 + gEVE + VE

VE

=

VOS

+

----V----D----D-----–---------V----S--S-

PSRR

+

------V----C---M---

CMRR

+

------V----R---E----F---

CMRR2

+

-----V---O----U----T-

AOL

+

TA



TC1

VED  INLDM VDMH – VDML

VE  INLCM VIVH – VIVL

Where:

PSRR, CMRR, CMRR2 and AOL are in

units of V/V

∆TA is in units of °C

TC1 is in units of V/°C

VDM = 0

DS20005318A-page 37

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