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MC100LVEL29
(Rev.:2016)

3.3 V ECL Dual Differential Data and Clock D Flip‐Flop with Set and Reset

ON Semiconductor 

MC100LVEL29

3.3 V ECL Dual Differential

Data and Clock D Flip‐Flop

with Set and Reset

Description

The MC100LVEL29 is a dual master-slave flip-flop. The device

features fully differential Data and Clock inputs as well as outputs.

The MC100LVEL29 is pin and functionally equivalent to the

MC100EL29. Data enters the master latch when the clock is LOW and

transfers to the slave upon a positive transition on the clock input.

The differential inputs have special circuitry which ensures device

stability under open input conditions. When both differential inputs

are left open the D input will pull down to VEE and the D input will

bias around VCC/2. The outputs will go to a defined state, however the

state will be random based on how the flip flop powers up.

Both flip flops feature asynchronous, overriding Set and Reset

inputs. Note that the Set and Reset inputs cannot both be HIGH

simultaneously.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

Features

• 1100 MHz Flip-Flop Toggle Frequency

• ESD Protection: > 2 kV Human Body Model

• 580 ps Typical Propagation Delays

• The 100 Series Contains Temperature Compensation

• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V

with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V

with VEE = −3.0 V to −3.8 V

• Internal Input Pulldown Resistors

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity: Level 3 (Pb-Free)

(For Additional Information, see Application Note AND8003/D)

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 313 Devices

• These Devices are Pb-Free, Halogen Free and are RoHS Compliant

www.onsemi.com

SOIC−20 WB

DW SUFFIX

CASE 751D−05

MARKING DIAGRAM*

20

100LVEL29

AWLYYWWG

1

A

= Assembly Location

WL = Wafer Lot

YY

= Year

WW = Work Week

G

= Pb-Free Package

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

Device

Package Shipping†

MC100LVEL29DWG

SOIC−20 WB 38 Units / Tube

(Pb-Free)

MC100LVEL29DWR2G SOIC−20 WB 1000 Tape & Reel

(Pb-Free)

†For information on tape and reel specifications, in-

cluding part orientation and tape sizes, please refer

to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2016

1

July, 2016 − Rev. 7

Publication Order Number:

MC100LVEL29/D

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