74HCT597D/AUJ(2016) 查看數據表（PDF） - NXP Semiconductors.
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74HCT597D/AUJ Datasheet PDF : 22 Pages
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Nexperia
74HC597; 74HCT597
8-bit shift register with input flip-flops
5. Pinning information
5.1 Pinning
+&
+&7
'
'
'
'
'
'
'
*1'
Fig 5. Pin configuration SO16, SSOP16 and TSSOP16
9&&
'
'6
3/
67&3
6+&3
05
4
DDD
5.2 Pin description
Table 2. Pin description
Symbol
GND
Q
MR
SHCP
STCP
PL
DS
D0, D1, D2, D3, D4, D5, D6, D7
VCC
Pin
8
9
10
11
12
13
14
15, 1, 2, 3, 4, 5, 6, 7
16
Description
ground (0 V)
serial data output
asynchronous master reset input (active LOW)
shift register clock input (LOW-to-HIGH, edge-triggered)
storage register clock input (LOW-to-HIGH, edge-triggered)
parallel load input (active LOW)
serial data input
parallel data inputs
supply voltage
74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© Nexperia B.V. 2017. All rights reserved
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