74HCT00BQ-Q100,115(2012) 查看數據表（PDF） - NXP Semiconductors.
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74HCT00BQ-Q100,115 Datasheet PDF : 15 Pages
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NXP Semiconductors
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
5. Pinning information
5.1 Pinning
74HC00-Q100
74HCT00-Q100
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
aaa-003147
Fig 4. Pin configuration SO14 and TSSOP14
74HC00-Q100
74HCT00-Q100
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
aaa-003148
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3. Function table[1]
Input
nA
nB
L
X
X
L
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Output
nY
H
H
L
74HC_HCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2012
© NXP B.V. 2012. All rights reserved.
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