74HCT00D-Q100 查看數據表（PDF） - NXP Semiconductors.
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74HCT00D-Q100 Datasheet PDF : 15 Pages
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Nexperia
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
Table 7. Dynamic characteristics …continued
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
Symbol Parameter
Conditions
Min
74HCT00-Q100
tpd
propagation delay nA, nB to nY; see Figure 6
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
CPD
power dissipation per package;
capacitance
VI = GND to VCC 1.5 V
[1]
-
-
[2]
-
[3]
-
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
25 C
Typ
12
10
-
22
40 C to +125 C Unit
Max Max
Max
(85 C) (125 C)
-
24
29 ns
-
-
- ns
-
29
22 ns
-
-
- pF
11. Waveforms
9,
Q$Q%LQSXW
*1'
92+
Q<RXWSXW
92/
90
W3+/
9<
W7+/
90
9;
W3/+
W7/+
Fig 6.
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Input to output propagation delays
DDL
Table 8. Measurement points
Type
Input
VM
74HC00-Q100
0.5VCC
74HCT00-Q100
1.3 V
Output
VM
0.5VCC
1.3 V
VX
0.1VCC
0.1VCC
VY
0.9VCC
0.9VCC
74HC_HCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2015
© Nexperia B.V. 2017. All rights reserved
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