74LV174D 查看數據表（PDF） - NXP Semiconductors.

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74LV174D

Hex D-type flip-flop with reset; positive-edge trigger

NXP Semiconductors. 

Philips Semiconductors

Hex D-type flip-flop with reset; positive edge-trigger

Product specification

74LV174

AC CHARACTERISTICS (Continued)

GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ

SYMBOL

PARAMETER

WAVEFORM

CONDITION

VCC(V)

1.2

th

Hold time

Dn to CP

Figure 3

2.0

2.7

3.0 to 3.6

4.5 to 5.5

2.0

fmax

Maximum clock

pulse frequency

Figure 1

2.7

3.0 to 3.6

4.5 to 5.5

NOTES:

1. Unless otherwise stated, all typical values are at Tamb = 25°C.

2. Typical value measured at VCC = 3.3V.

3. Typical value measured at VCC = 5.0V.

LIMITS

–40 to +85 °C

MIN TYP1 MAX

–

–10

–

5

–4

–

5

–2

–

5

–22

–

5

–13

14

40

–

19

58

–

24

702

–

36

1003

LIMITS

–40 to +125 °C

MIN MAX

–

–

5

–

5

–

5

–

5

12

–

16

–

20

–

30

UNIT

ns

MHz

AC WAVEFORMS

VM = 1.5V at VCC w 2.7V v 3.6V

VM = 0.5V * VCC at VCC t 2.7V and w 4.5V

VOL and VOH are the typical output voltage drop that occur with the

output load.

Vi

VI

CP INPUT

GND

VOH

Qn OUTPUT

VOL

1/fmax

VM

tw

tPHL

VM

tPLH

SV00351

Figure 1. The clock (CP) to output (Qn) propagation delays, the

clock pulse width, and the maximum clock pulse frequency.

MR INPUT

GND

Vi

CP INPUT

GND

VOH

Qn OUTPUT

VOL

VM

tw

tPHL

VM

trem

VM

SV00352

Figure 2. The master reset (MR) pulse width, the master reset

to output (Qn) propagation delay and the master reset to clock

removal time.

1998 May 20

7

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