SST25PF080B 查看數據表（PDF） - Microchip Technology
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SST25PF080B Datasheet PDF : 32 Pages
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SST25PF080B
bit command, 70H, must be executed prior to initiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first exe-
cute WRDI instruction, 04H, to reset the Write-Enable-
Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.
CE#
MODE 3
SCK MODE 0
0 1 23456 7
FIGURE 4-6:
SI
70
MSB
SO
HIGH IMPEDANCE
25137 EnableSO.0
ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
MODE 3
SCK MODE 0
0 1 23456 7
FIGURE 4-7:
SI
80
MSB
SO
HIGH IMPEDANCE
25137 DisableSO.0
DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
DS25134A-page 10
2012 Microchip Technology Inc.
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