LF3304QC10 查看數據表（PDF） - LOGIC Devices

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LF3304QC10

Dual Line Buffer/FIFO

LOGIC Devices 

DEVICES INCORPORATED

LF3304

Dual Line Buffer/FIFO

FIFO MODE

OPERATION

Initialization

Upon power-up, the LF3304 requires

the initialization of the internal read

and write address pointers. This

initialization sequence can be done

by either a Flag Enable Reset or a

Flag Disable Reset.

A Flag Enable Reset will force the

FIFO to operate in a ‘Flag Enabled’

mode. In this mode, writing will be

disabled when FFx is LOW and

reading is disabled when EFx is

LOW. Any ‘write beyond full’ event

or ‘read beyond empty’ event will be

disabled. Note: in an ‘empty’ state,

the last data word read from the

FIFO is held on the output bus until

the next valid read cycle.

A Flag Disable Reset will force the

FIFO to operate in a ‘Flag Disabled’

mode. In this mode, the user is

allowed to write over previously un-

read data and read out previously

read data. Consequently, any

enabled write or read is valid thus

allowing the write and read pointers

to ‘wrap-around’. Note: due to the

nature of this mode, the flag status

should be disregarded. For example,

as the 4096th data word is written

into the FIFO, assuming that no

preceding read cycles have occured,

FFx will be driven LOW thus indicat-

ing a ‘full’state. While the FIFO is

still in this ‘full’ state, the next

enabled write will access address

000H, thus writing over data that

has not yet been read out.

Flag Enable Reset

A Flag Enable Reset resets the read

and write pointers and enables the

flags to control the reading and

writing of data according to the Full

Flag and Empty Flag conditions. A

Flag Enable Reset occurs when the

following conditions are met:

1. RWA/RWB must be LOW for at

least one WCLKA/WCLKB cycle.

2. RRA/RRB must be LOW for at

least one RCLKA/RCLKB cycle.

3. WENx and RENx must be HIGH

during the above two conditions

plus one addition write or read

cycle (which ever is longer).

The Flag Enable Reset condition can

be disabled if one of the two Flag

Disable Reset conditions are applied.

Flag Disable Reset

A Flag Disable Reset resets the read

and write pointers and disables the

flags from controlling the reading

and writing of data. A Flag Disable

Reset occurs when the following

conditions are met:

1. RWA/RWB must be LOW for at

least one WCLKA/WCLKB cycle

while WENx is LOW.

2. RRA/RRB must be LOW for at

least one RCLKA/RCLKB cycle

while RENx is LOW.

Configuration of Programmable Flags

In order to load a FIFO A Program-

mable Flag Register, a rising edge of

WCLKA, while WENA is LOW,

latches AIN11-0 into either the PAFA

or PAEA Register - depending on the

states of ADDRA and LDA (See

Table 2).

In order to load a FIFO B Program-

mable Flag Register, a rising edge of

WCLKB, while WENB is LOW,

latches BIN11-0 into either the PAFB

or PAEB Register - depending on the

states of ADDRB and LDB (See Table

2). See the Figure labeled “Program-

mable Flag Load Timing.”

Video Imaging Products

5

08/16/2000–LDS.3304-F

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