CY8C4245AZQ-432 查看數據表（PDF） - Cypress Semiconductor

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CY8C4245AZQ-432

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 4: PSoC 4100 Family

Datasheet

PSoC 4100

32-bit

AHB-Lite

System Resources

Power

Sleep Control

W IC

POR LVD

REF BOD

PWRSYS

N V L atc he s

Clock

Clock Control

WDT

IM O

ILO

Reset

Reset Control

XRES

Test

DFT Logic

DFT Analog

CPU Subsystem

SWD

Cortex

M0

24 MHz

FAST MUL

NVIC, IRQMX

Figure 2. Block Diagram

FLASH

Up to 32 kB

Read Accelerator

SRAM

Up to 4 kB

SRAM Controller

ROM

4 kB

ROM Controller

Peripherals

PCLK

System Interconnect (Single Layer AHB)

Peripheral Interconnect (M MIO)

Program mable

Analog

SAR ADC

(12-bit)

x1

SMX

CTBm

2x OpAmp x1

Port Interface & Digital System Interconnect (DSI)

Power Modes

Active/Sleep

Deep Sleep

Hibernate

IO Subsystem

The PSoC 4100 devices include extensive support for

programming, testing, debugging, and tracing both hardware

and firmware.

The ARM Serial_Wire Debug (SWD) interface supports all

programming and debug features of the device.

Complete debug-on-chip functionality enables full device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator Integrated Development Environment (IDE)

provides fully integrated programming and debug support for the

PSoC 4100 devices. The SWD interface is fully compatible with

industry standard third party tools. With the ability to disable

debug features, with very robust flash protection, and by allowing

customer-proprietary functionality to be implemented in on-chip

programmable blocks, the PSoC 4100 family provides a level of

High Speed I/O Matrix

36x GPIOs

security not possible with multi-chip application solutions or with

microcontrollers.

The debug circuits are enabled by default and can only be

disabled in firmware. If not enabled, the only way to re-enable

them is to erase the entire device, clear flash protection, and

reprogram the device with new firmware that enables debugging.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. Because all programming, debug, and test inter-

faces are disabled when maximum device security is enabled,

PSoC 4100 with device security enabled may not be returned for

failure analysis. This is a trade-off the PSoC 4100 allows the

customer to make.

Document Number: 001-87220 Rev. *J

Page 4 of 43

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