CY8C4245FNQ-483 查看數據表（PDF） - Cypress Semiconductor

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CY8C4245FNQ-483

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 4: PSoC 4100 Family

Datasheet

Functional Definition

CPU and Memory Subsystem

CPU

The Cortex-M0 CPU in PSoC 4100 is part of the 32-bit MCU

subsystem, which is optimized for low power operation with

extensive clock gating. It mostly uses 16-bit instructions and

executes a subset of the Thumb-2 instruction set. This enables

fully compatible binary upward migration of the code to higher

performance processors such as the Cortex-M3 and M4, thus

enabling upward compatibility. The Cypress implementation

includes a hardware multiplier that provides a 32-bit result in one

cycle. It includes a nested vectored interrupt controller (NVIC)

block with 32 interrupt inputs and also includes a Wakeup

Interrupt Controller (WIC), which can wake the processor up

from Deep Sleep mode allowing power to be switched off to the

main processor when the chip is in Deep Sleep mode. The

Cortex-M0 CPU provides a Non-Maskable Interrupt input (NMI),

which is made available to the user when it is not in use for

system functions requested by the user.

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a two-wire form of JTAG; the debug

configuration used for PSoC 4100 has four break-point

(address) comparators and two watchpoint (data) comparators.

Flash

PSoC 4100 has a flash module with a flash accelerator tightly

coupled to the CPU to improve average access times from the

flash block. The flash block is designed to deliver 0 wait-state

(WS) access time at 24 MHz. Part of the flash module can be

used to emulate EEPROM operation if required.

The PSoC 4200 Flash supports the following flash protection

modes at the memory subsystem level:

■ Open: No Protection. Factory default mode in which the

product is shipped.

■ Protected: User may change from Open to Protected. This

mode disables Debug interface accesses. The mode can be

set back to Open but only after completely erasing the Flash.

■ Kill: User may change from Open to Kill. This mode disables

all Debug accesses. The part cannot be erased externally, thus

obviating the possibility of partial erasure by power interruption

and potential malfunction and security leaks. This is an irrecvo-

cable mode.

In addition, row-level Read/Write protection is also supported to

prevent inadvertent Writes as well as selectively block Reads.

Flash Read/Write/Erase operations are always available for

internal code using system calls.

SRAM

SRAM memory is retained during Hibernate.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

System Resources

Power System

The power system is described in detail in the section Power on

page 15. It provides assurance that voltage levels are as

required for each respective mode and either delay mode entry

(on power-on reset (POR), for example) until voltage levels are

as required for proper function or generate resets (brown-out

detect (BOD)) or interrupts (low-voltage detect (LVD)). The

PSoC 4100 operates with a single external supply over the range

of 1.71 V to 5.5 V and has five different power modes, transitions

between which are managed by the power system. PSoC 4100

provides Sleep, Deep Sleep, Hibernate, and Stop low-power

modes.

Clock System

The PSoC 4100 clock system is responsible for providing clocks

to all subsystems that require clocks and for switching between

different clock sources without glitching. In addition, the clock

system ensures that no metastable conditions occur.

The clock system for PSoC 4100 consists of the internal main

oscillator (IMO) and the internal low-power oscillator (ILO) and

provision for an external clock.

Figure 3. PSoC 4100 MCU Clocking Architecture

IMO

EXTCLK

HFCLK

ILO

LFCLK

HFCLK

Prescaler

SYSCLK

Analog

Divider

Peripheral

Dividers

SAR clock

PERXYZ _CLK

The HFCLK signal can be divided down (see PSoC 4100 MCU

Clocking Architecture) to generate synchronous clocks for the

analog and digital peripherals. There are a total of 12 clock

dividers for PSoC 4100, each with 16-bit divide capability. The

analog clock leads the digital clocks to allow analog events to

occur before digital clock-related noise is generated. The 16-bit

capability allows a lot of flexibility in generating fine-grained

frequency values and is fully supported in PSoC Creator.

Document Number: 001-87220 Rev. *J

Page 5 of 43

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