LTC4440 查看數據表（PDF） - Linear Technology
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LTC4440 Datasheet PDF : 14 Pages
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LTC4440
Applications Information
Overview
The LTC4440 receives a ground-referenced, low voltage
digital input signal to drive a high side N-channel power
MOSFET whose drain can float up to 100V above ground,
eliminating the need for a transformer between the low
voltage control signal and the high side gate driver. The
LTC4440 normally operates in applications with input
supply voltages (VIN) up to 80V, but is able to withstand
and continue to function during 100V, 100ms transients
on the input supply.
The powerful output driver of the LTC4440 reduces the
switching losses of the power MOSFET, which increase
with transition time. The LTC4440 is capable of driving a
1nF load with 10ns rise and 7ns fall times using a boot-
strapped supply voltage VBOOST–TS of 12V.
Input Stage
The LTC4440 employs TTL/CMOS compatible input thresh-
olds that allow a low voltage digital signal to drive standard
power MOSFETs. The LTC4440 contains an internal voltage
regulator that biases the input buffer, allowing the input
thresholds (VIH = 1.6V, VIL = 1.25V) to be independent of
variations in VCC. The 350mV hysteresis between VIH and
VIL eliminates false triggering due to noise during switch-
ing transitions. However, care should be taken to keep this
pin from any noise pickup, especially in high frequency,
high voltage applications. The LTC4440 input buffer has a
high input impedance and draws negligible input current,
simplifying the drive circuitry required for the input.
Output Stage
A simplified version of the LTC4440’s output stage is shown
in Figure 3 . The pull-down device is an N-channel MOSFET
(N1) and the pull-up device is an NPN bipolar junction
transistor (Q1). The output swings from the lower rail (TS)
to within an NPN VBE (~ 0.7V) of the positive rail (BOOST).
This large voltage swing is important in driving external
power MOSFETs, whose RDS(ON) is inversely proportional
to its gate overdrive voltage (VGS – VTH).
The LTC4440’s peak pull-up (Q1) current is 2.4A while the
pull-down (N1) resistance is 1.5Ω. The low impedance
of N1 is required to discharge the power MOSFET’s gate
capacitance during high-to-low signal transitions. When the
BOOST
VIN
UP TO 100V
LTC4440
Q1
TG
N1
TS
CGD
POWER
MOSFET
CGS
LOAD
INDUCTOR
V 4440 F03
–
Figure 3. Capacitance Seen by TG During Switching
power MOSFET’s gate is pulled low (gate shorted to source
through N1) by the LTC4440, its source (TS) is pulled low
by its load (e.g., an inductor or resistor). The slew rate
of the source/gate voltage causes current to flow back to
the MOSFET’s gate through the gate-to-drain capacitance
(CGD). If the MOSFET driver does not have sufficient sink
current capability (low output impedance), the current
through the power MOSFET’s CGD can momentarily pull
the gate high, turning the MOSFET back on.
A similar scenario exists when the LTC4440 is used to drive
a low side MOSFET. When the low side power MOSFET’s
gate is pulled low by the LTC4440, its drain voltage is pulled
high by its load (e.g., inductor or resistor). The slew rate
of the drain voltage causes current to flow back to the
MOSFET’s gate through its gate-to-drain capacitance. If
the MOSFET driver does not have sufficient sink current
capability (low output impedance), the current through
the power MOSFET’s CGD can momentarily pull the gate
high, turning the MOSFET back on.
Rise/Fall Time
Since the power MOSFET generally accounts for the ma-
jority of the power loss in a converter, it is important to
quickly turn it on or off, thereby minimizing the transition
time in its linear region. The LTC4440 can drive a 1nF load
with a 10ns rise time and 7ns fall time.
The LTC4440’s rise and fall times are determined by the
peak current capabilities of Q1 and N1. The predriver that
drives Q1 and N1 uses a nonoverlapping transition scheme
to minimize cross-conduction currents. N1 is fully turned
off before Q1 is turned on and vice versa.
4440fa
For more information www.linear.com//LTC4440
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