STP16CP05TTR(2006) 查看數據表（PDF） - STMicroelectronics
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STP16CP05TTR Datasheet PDF : 26 Pages
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Timing diagrams
5
Timing diagrams
STP16CP05
Note:
Table 8. Truth Table
CLOCK
LE
/OE
H
L
L
L
H
L
X
L
X
L
SERIAL-
IN
OUT0 ............. OUT7 ................ OUT15
Dn
Dn + 1
Dn + 2
Dn + 3
Dn + 3
Dn ..... Dn - 7 ..... Dn -15
No Change
Dn - 2 ..... Dn - 5 ..... Dn -13
Dn - 2 ..... Dn - 5 ..... Dn -13
ON
SDO
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
OUT0 to OUT15 = ON when Dn = H; OUT0 to OUT15 = OFF when Dn = L.
Figure 7. Timing diagram
Note:
The latches circuit holds data when the LE terminal is Low.
1 When LE terminal is at High level, latch circuit hold the data it passes from the input to the
output.
2 When OE terminal is at Low level, output terminals OUT0 to OUT15 respond to the data,
either ON or OFF.
3 When OE terminal is at High level, it switches off all the data on the output terminal.
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