MCF53017CMJ240 查看數據表（PDF） - Freescale Semiconductor

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MCF53017CMJ240

MCF5301x Data Sheet

Freescale Semiconductor 

Hardware Design Considerations

3.3V

2.5V

1.8V

1.2V

1

Supplies Stable

EVDD, USBVDD (3.3V)

SDVDD (2.5V - DDR)

SDVDD (1.8V - DDR)

IVDD, PVDD

2

0

Time

Notes:

1 IVDD should not exceed EVDD, SDVDD or PVDD by more than 0.4V at any time, including power-up.

2 Recommended that IVDD/PVDD should track EVDD/SDVDD up to 0.9V then separate for completion of ramps

3 Input voltage must not be greater than the supply voltage (EVDD, SDVDD, IVDD, or PVDD) by more than 0.5V

at any time, including during power-up.

4 Use 1 microsecond or slower rise time for all supplies.

Figure 3. Supply Voltage Sequencing and Separation Cautions

3.3.1 Power Up Sequence

If EVDD/SDVDD are powered up with the IVDD at 0V, then the sense circuits in the I/O pads will cause all pad output drivers

connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up

before IVDD must power up. IVDD should not lead the EVDD, SDVDD or PVDD by more than 0.4V during power ramp up or

there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1

microsecond to avoid turning on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 microsecond or slower rise time for all supplies.

2. IVDD/PVDD and EVDD/SDVDD should track up to 0.9V and then separate for the completion of ramps with

EVDD/SDVDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage

regulator.

3.3.2 Power Down Sequence

If IVDD/PVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance

state. There is no limit on how long after IVDD and PVDD power down before EVDD or SDVDD must power down. IVDD should

not lag EVDD, SDVDD, or PVDD going low by more than 0.4V during power down or there will be undesired high current in

the ESD protection diodes. There are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IVDD/PVDD to 0V.

2. Drop EVDD/SDVDD supplies.

MCF5301x Data Sheet, Rev. 5

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

7

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