EL8171FSZ(2007) 查看數據表（PDF） - Intersil
零件编号
产品描述 (功能)
生产厂家
EL8171FSZ
(Rev.:2007)
(Rev.:2007)
Intersil
EL8171FSZ Datasheet PDF : 14 Pages
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EL8171, EL8172
Typical Performance Curves V+ = 5V, V- = 0V,VCM = 2.5V, VEN = V-, RL = Open, unless otherwise specified. (Continued)
0.70
0.65
N = 1000
0.60
0.55
0.50
0.45
0.40
0.35
MAX
MEDIAN
MIN
0.65
N = 1500
0.60
MAX
0.55
MEDIAN
0.50
0.45
MIN
0.30
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
0.40
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 37. EL8171 -SLEW RATE vs TEMPERATURE,
INPUT = ±0.015V @ GAIN + 100
FIGURE 38. EL8172 -SLEW RATE vs TEMPERATURE,
INPUT = ±0.015V @ GAIN + 100
Pin Descriptions
EL8171/EL8172
1
PIN NAME
EN
2
IN-
3
IN+
4
V-
5
FB-
8
FB+
7
V+
6
VOUT
EQUIVALENT CIRCUIT
PIN FUNCTION
Circuit 2
Active LOW logic pins. When pulled above 2V, the corresponding channel turns off
and OUT is high impedance. A channel is enabled when pulled below 0.8V. Built
in pull downs define each EN pin LOW when left floating.
Circuit 1A, Circuit 1B
Circuit 1A, Circuit 1B
High impedance input terminals. EL8172 input circuit is shown in Circuit 1A, and
the EL8171 input circuit is shown in Circuit 1B. EL8171: to avoid offset drift, it is
recommended that the terminals are not overdriven beyond 1V and the input
current must never exceed 5mA.
Circuit 4
Negative supply terminal.
Circuit 1A, Circuit 1B
Circuit 1A, Circuit 1B
High impedance feedback terminals. EL8172 input circuit is shown in Circuit 1A,
and the EL8171 input circuit is shown in Circuit 1B. EL8171: to avoid offset drift, it
is recommended that the terminals are not overdriven beyond 1V and the input
current must never exceed 5mA.
Circuit 4
Positive supply terminal.
Circuit 3
Output Voltage.
IN-
FB-
CIRCUIT 1A
IN-
FB-
V+
IN+
FB+
V-
V+
IN+
FB+
V-
V+
LOGIC
PIN
V-
CIRCUIT 2
V+
OUT
V-
CIRCUIT 3
V+
CAPACITIVELY
COUPLED
ESD CLAMP
V-
CIRCUIT 4
CIRCUIT 1B
10
FN6293.3
August 3, 2007
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