FM1608B-PG 查看數據表（PDF） - Cypress Semiconductor

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FM1608B-PG

F-RAM

Cypress Semiconductor 

Write Cycle Timing - /WE Controlled Timing

CE

A(12:0)

WE

tAH

tAS

tWS

tWC

tCA

tC W

tWP

OE

DQ(7:0)

out

DQ(7:0)

in

tWZ

tDS

Power Cycle Timing

VDD

CE

VDD (min)

t PD

t PC

VIH (min)

VIH (min)

FM1608B (PDIP)

tPC

tWH

tWX

tDH

VDD (min)

t PU

VIL (max)

Power Cycle Timing (TA = 0 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified)

Symbol Parameter

Min

Max Units

tPU

VDD(min) to First Access Start

tPD

Last Access Complete to VDD(min)

tVR

VDD Rise Time

tVF

VDD Fall Time

10

-

ms

0

-

s

30

-

s/V

30

-

s/V

Notes

1 Slope measured at any point on VDD waveform.

2 This parameter has been characterized and not 100% tested at 0°C.

Notes

2

1,2

1,2

Document Number: 001-86599 Rev. **

Page 9 of 12

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