LTC1473 查看數據表（PDF） - Linear Technology

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LTC1473

Dual PowerPath Switch Driver

Linear Technology 

LTC1473

PIN FUNCTIONS

IN1 (Pin 1): Logic Input of Gate Drivers GA1 and GB1. IN1

is disabled when IN2 is high or DIODE is low.

IN2 (Pin 2): Logic Input of Gate Drivers GA2 and GB2. IN2

is disabled when IN1 is high or DIODE is low.

DIODE (Pin 3): “2-Diode Mode” Logic Input. DIODE over-

rides IN1 and IN2 by forcing the two back-to-back

external N-channel MOSFET switches to mimic two

diodes.

TIMER (Pin 4): Fault Timer. A capacitor connected from

this pin to GND programs the time the MOSFET switches

are allowed to be in current limit. To disable this function,

Pin 4 can be grounded.

V+ (Pin 5): Input Supply. Bypass this pin with at least a 1µF

capacitor.

VGG (Pin 6): Gate Driver Supply. This high voltage supply

is intended only for driving the internal micropower gate

drive circuitry. Do not load this pin with any external

circuitry. Bypass this pin with at least 1µF.

SW (Pin 7): Open Drain of an internal N-Channel MOSFET

Switch. This pin drives the bottom of the VGG switching

regulator inductor which is connected between this pin

and the V+ pin.

GND (Pin 8): Ground.

GA2, GB2 (Pins 11, 9): Switch Gate Drivers. GA2 and GB2

drive the gates of the second back-to-back external

N-channel switches.

SAB2 (Pin 10): Source Return. The SAB2 pin is connected

to the sources of SW A2 and SW B2. A small pull-down

current source returns this node to 0V when the switches

are turned off.

SENSE – (Pin 12): Inrush Current Input. This pin should be

connected directly to the bottom (output side) of the low

value current sense resistor in series with the two input

power selector switch pairs, SW A1/B1 and SW A2/B2, for

detecting and controlling the inrush current into and out of

the power supply sources and the output capacitor.

SENSE + (Pin 13): Inrush Current Input. This pin should be

connected directly to the top (switch side) of the low value

current sense resistor in series with the two input power

selector switch pairs, SW A1/B1 and SW A2/B2, for

detecting and controlling the inrush current into and out of

the power supply sources and the output capacitor. Cur-

rent limit is invoked when (VSENSE + – VSENSE–) exceeds

±0.2V.

GA1, GB1 (Pins 16, 14): Switch Gate Drivers. GA1 and

GB1 drive the gates of the first back-to-back external

N-channel switches.

SAB1 (Pin 15): Source Return. The SAB1 pin is connected

to the sources of SW A1 and SW B1. A small pull-down

current source returns this node to 0V when the switches

are turned off.

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