74AHC138D,112 查看數據表（PDF） - NXP Semiconductors.
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74AHC138D,112 Datasheet PDF : 17 Pages
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74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 4 — 2 April 2014
Product data sheet
1. General description
The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three
binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight
mutually exclusive outputs (Y0 to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74AHC138; 74AHCT138 devices and one
inverter. The 74AHC138; 74AHCT138 can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data input and the remaining enable
inputs as strobes. Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
2. Features and benefits
Balanced propagation delays
All inputs have Schmitt-trigger action
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Inputs accepts voltages higher than VCC
For 74AHC138 only: operates with CMOS input levels
For 74AHCT138 only: operates with TTL input levels
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
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