VSC7130RC(2000) 查看數據表（PDF） - Vitesse Semiconductor

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VSC7130RC
(Rev.:2000)

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7130

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Implementing reference clock distribution in multi-node systems can be difficult and expensive if optimal

signal quality is to be achieved. In order to reduce this burden, the VSC7130 has a flexible reference input

buffer which can be either single-ended TTL, differential PECL or LVDS. If single-ended, REFI+ should be

connected to the clock source and REFI- should be left unconnected. REFI- is biased to VDD/2 for TTL

thresholds. If a PECL or LVDS source is used, connect the positive side to REFI+ and the negative side to

REFI-. In order to provide the reference clock to multiple devices, a reference clock output, REFO+/-, is pro-

vided which is just an LVDS buffered version of REFI+/-. In this way, multiple VSC7130s may be daisy

chained together with the REFO driving the REFI of the next device. When REFO is driving REFI, a 100

ohm resistor should be connected between REFI+ and REFI-.

The reference clock is used by the clock multiplier unit (CMU) in order to generate the internal baud rate

clock. In order to maximize signal quality of the TX and SO outputs, the REFI input should be of the highest

quality possible with sharp edges and low jitter. Duty cycle distortion is not very important since only the rising

edge of REFI is used. The CMU is a high performance analog PLL which multiplies the reference clock fre-

quency by 20 or 10 depending on HALF/FULL. A single external 0.1uF capacitor must be connected between

the CAP0 and CAP1 pins in order to control the loop bandwidth of the CMU. Separate power (VDDA) and

ground (VSSA) are provided in order to allow a separately filtered power supply to reduce noise.

Input and Output Buffers, Analog Signal Detection, Cable Equalization

The RX0+/-, RX1+/- and SI+/- differential inputs are high performance input buffers which amplify the

incoming signal. Furthermore, a cable equalization circuit is included in the input buffer which accentuates

high frequency signals in order to compensate for the high frequency loss found in copper cables and traces.

This cable equalization circuit enhances the ability of the VSC7130 to reliably receive serial inputs which have

been degraded with jitter. The RX1+/- input buffer also includes an analog signal detection circuit which indi-

cates, when HIGH, that the differential input is at least 375mV. If the input amplitude is less than 200mV the

output will be LOW. If the input is between 200mV and 375mV, the output is indeterminate. The output of this

signal is processed further in the Signal Detection circuitry described elsewhere.

If the Two-Wire Interface is not used, R1/0 directly controls the RX0 and RX1 input buffers and Cable

Equalization is enabled in SI, RX0 and RX1. If the Two-Wire Interface is used, microcontroller control allows

enabling or disabling of the cable equalization circuit.

Please refer to the “VSC7130 User’s Manual” for a more complete description of the input and output

buffer controls and cable equalization controls.

G52297-0, Rev. 2.3

1/17/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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