MG64PB16 查看數據表（PDF） - Oki Electric Industry

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MG64PB16

0.25µm Embedded DRAM/Customer Structured Arrays

Oki Electric Industry 

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG63P/64P/65P s

Reconfigurable SDRAM Core

Data Input

(128 bit)

Data Output

(128 bit)

Type I: 512 Kb (1 bank) - 8 Mb (16 bank); 512 Kb increment

Data Input

(256 bit)

Data Output

(256 bit)

Type I I: 1Mb (1 bank) - 16 Mb (16 bank); 1Mb increment

Figure 10. SDRAM Compiler

SDRAM Core Functional Specification

Density

Bit Organization

Maximum Clock Rate

VDD

CAS Latency

Burst Length

Write Latency

DQM Latency

Refresh

Macro Pinout

Type I: 512kb (1BK) - 8Mb (16BK) by 512 kb

Type II: 1 Mb (1BK) - 16 Mb (16 BK) by 1 Mb

x16/x32/x64/x128/x256 (x256 Type II Only)

100 MHz

2.5V

2

1

0

0: Write, 2: Read

512 Refresh cycles/8 ms

CLK, ACT, PRE, RD, WR, AX(8:0), AY(2:0), BAX(2:0), BAY(2:0), DQM (15:0), D(127:0),

Q9127:0), REF, RST, test pins

Oki Semiconductor

5

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