LTC1590 查看數據表（PDF） - Linear Technology

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LTC1590

Dual Serial 12-Bit Multiplying DAC

Linear Technology 

LTC1590

APPLICATIONS INFORMATION

Op Amp Selection

To maintain the excellent accuracy and stability of the

LTC1590 thought should be given to op amp selection.

Fortunately, the sensitivity of INL and DNL to op amp offset

has been significantly reduced compared to competing

parts of this type. The op amp’s VOS causes DAC output

offset. In addition, because the DAC’s equivalent output

resistance RO changes as a function of code, there is a

code-dependent DAC output error proportional to VOS. For

fixed reference applications this causes gain, INL and DNL

error. For multiplying applications, a code-dependent, DC

output voltage error is seen. At zero scale the DAC output

error is equal to the op amp offset, and at full scale the

output error is equal to twice the op amp offset. For

example, a 1mV op amp offset will cause a 0.41LSB zero-

scale error and a 0.82LSB full-scale error with a 10V full-

scale range. The offset caused INL error is approximately

0.4 times the op amp VOS and DNL error is 0.07 times op

amp VOS. For the same example of 1mV op amp VOS and

10V full-scale range, the INL degradation will be 0.17LSB

and DNL degradation will be 0.03LSB.

Op amp bias current causes only an offset error equal to

(IBIAS)(RFB) ≈ (IBIAS)(11kΩ). For example, a 100nA op

amp bias current causes a 1.1mV DAC offset, or 0.45LSB

for a 10V full-scale range. It is important to note that

connecting the op amp noninverting input to ground

through a resistor will not cancel bias current errors and

should never be done! Similarly an offset caused by op

amp bias current should not be adjusted by using the op

amp null pins since this increases offset between DAC

OUT1 and OUT2 pins, causing INL, DNL and gain errors.

If op amp offset error adjustment is required, the op amp

input offset voltage (the voltage difference between OUT1

and OUT2) should be nulled.

Grounding

As with any high precision data converter, clean ground-

ing is important. A low impedance analog ground plane

and star grounding should be used. OUT2 carries the

complementary DAC output current and should be tied to

the star ground with as low a resistance as possible. Other

ground points that must be tied to the star ground point

include the VREF input ground, the op amp noninverting

input(s) and the VOUT ground reference point.

TYPICAL APPLICATIONS

5V

0.1µF 16

DATA IN

SERIAL CLOCK

CHIP SELECT/DAC LOAD

DATA OUT

CLEAR

13 DIN

14 CLK

11 CS/LD

12 DOUT

15 CLR

24-BIT

SHIFT

REG

AND

LATCH

7 AGND

10 DGND

Dual Programmable Attenuator

VIN B

±10V

1

2

VREF B

RFB B

DAC B

OUT1 B 3

OUT2 B 4

15V

33pF

2–

8

1/2

LT1358

3+

LTC1590

DAC A

VREF A

RFB A

9

8

VIN A

±10V

OUT2 A 5

OUT1 A 6

5+

1/2

LT1358

6–

4

33pF

–15V

0.01µF

1

VOUT B

( ) VOUT = –VIN

D

4096

7

VOUT A

0.01µF

1590 TA07

9

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