MIC2563A-0BSM(1997) 查看數據表（PDF） - Micrel
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MIC2563A-0BSM Datasheet PDF : 10 Pages
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MIC2563A
A
VCC
Enable
0
VCC to 3.3V
5V
3.3V
VCC
Output
t1
t3
0
B
C
VCC OFF
VCC to 5V
t7
t5
t2
t4
D
VCC OFF
t8
t6
Micrel
Figure 2. MIC2563A VCC Timing Diagram. VCC Enable is shown generically: refer to the timing tables (below) for
specific control logic input. At time A, VCC is programmed to 3.3V. At B, VCC is disabled. At C, VCC is programmed
to 5V. And at D, VCC is disabled. RL = 10Ω
MIC2563A-0 Control Logic Table
VCC5_EN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VCC3_EN
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
EN1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
EN0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VCC OUT
VPP OUT
Clamped to Ground
Clamped to Ground
Clamped to Ground
Clamped to Ground
3.3
3.3
3.3
3.3
5
5
5
5
3.3
3.3
3.3
3.3
High Z
High Z
High Z
Clamped to Ground
High Z
3.3
12
Clamped to Ground
High Z
5
12
Clamped to Ground
High Z
3.3
5
Clamped to Ground
2-52
1997
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