MC145740F 查看數據表（PDF） - Motorola => Freescale

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MC145740F

Dual Tone Multiple Frequency Line Interface

Motorola => Freescale 

SERIAL DATA INTERFACE

REGISTER MAP DESCRIPTION

The timing diagram of the 14–bit control register input and

the 4–bit status register output is shown in Figure 4. When

the R/W pin is at logic low (write is selected), the control reg-

ister is enabled. The 14 bits of data are captured into the con-

trol register at the rising edge of SCK. The 14 bits of data in

the control register are transferred to the mode control logic

at logic high to the EN pin, and then the function mode is im-

mediately changed.

When the R/W pin is at logic high (read is selected), the

status register is enabled to read out the decoded DTMF

data. At the rising edge of EN, the four bits of data in the

DTMF decoder are loaded into the status register, and the

first bit (D0) is presented on the DATA pin. The next three bits

are shifted out by following rising edges of CLK (see Figure

4).

FUNCTION MODE (M2 – M0)

These three bits (M2 – M0) determine the function mode

shown in Table 1.

Table 1. Function Mode Truth Table

M2

M1

M0

Function Mode

0

0

0

DTMF Receive

0

0

1

DTMF Transmit

0

1

0

Single Tone Transmit

0

1

1

Power Down 1

1

0

0

1

0

1

Power Down 2

Analog Loopback

DTMF Receive Mode (M2 – M0 = 0, 0, 0)

The DTMF receiver is enabled. The transmitter is disabled.

DTMF Transmit Mode (M2 – M0 = 0, 0, 1)

The DTMF tone generator is enabled. The receiver is dis-

abled.

Single Tone Mode (M2 – M0 = 0, 1, 0)

The transmitter generates one of the eight frequencies of

DTMF tones. The receiver is disabled.

Power Down Mode (Mode 1: M2 – M0 = 0, 1, 1;

Mode 2: M2 – M0 = 1, 0, 0)

In Power Down Mode 1, all internal circuits except for the

oscillator are disabled, so that all output pins except for the

X1 are in high–impedance state. The device current is

decreased to 500 µA (max). In Power Down Mode 2, all inter-

nal circuits are disabled, so all output pins are in high imped-

ance state. The device current is decreased to 1 µA (max).

Analog Loopback Mode (M2 – M0 = 1, 0, 1)

The transmitter output is internally connected to the

receiver input.

TRANSMIT SQUELCH (SQ)

When the SQ bit is 1, the DTMF and single tone transmis-

sion are disabled (squelch is selected). However, the trans-

mit squelch does not affect the external signal input from

DSI.

DTMF TONE DETECT/REJECT TIME (CD1, CD0)

The CD1 and CD0 bits determine DTMF tones detect time

(ton) and release time (toff) of the DV pin, as shown in

Table 2. The timing diagram is shown in Figure 2.

Table 2. DTMF Detect Time Truth Table

CD1

0

CD0

0

ton (ms)

toff (ms)

Reserved

0

1

20

20

1

0

30

30

1

1

40

20

CONTROL REGISTER (R/W = “L”)

FUNCTION MODE

: 3 BITS

M2

M1

M0

TRANSMIT SQUELCH

: 1 BIT

SQ

DTMF DETECT TIME

: 2 BITS

CD1

CD0

TRANSMIT ATTENUATOR/AGC GAIN : 4 BITS

A3

A2

A1

A0

TRANSMIT FREQUENCY

: 4 BITS

T3

T2

T1

T0

STATUS REGISTER (R/W = “H”)

RECEIVED TONE FREQUENCY

: 4 BITS

D3

D2

D1

D0

MC145740

8

MOTOROLA

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