AD823AR(1995) 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD823AR
(Rev.:1995)

Dual, 16 MHz, Rail-to-Rail FET Input Amplifier

Analog Devices 

RL = 100kΩ

CL = 50pF

10V

AD823

–10V

5V

500ns

Figure 34. Pulse Response, VS = ±15 V, G = +1

THEORY OF OPERATION

This AD823 is fabricated on Analog Devices’ proprietary

complementary bipolar (CB) process that enables the construc-

tion of pnp and npn transistors with similar fTs in the 600 MHz

to 800 MHz region. In addition, the process also features

N-channel JFETs, which are used in the input stage of the AD823.

These process features allow the construction of high frequency,

low distortion op amps with picoampere input currents. This

design uses a differential-output input stage to maximize band-

width and headroom (see Figure 35). The smaller signal swings

required on the S1P, S1N outputs reduce the effect of nonlinear

currents due to junction capacitances and improve the distortion

performance. With this design harmonic distortion of better

than –91 dB @ 20 kHz into 600 Ω with VOUT = 4 V p-p on a

single 5 volt supply is achieved. The complementary common-

emitter design of the output stage provides excellent load drive

without the need for emitter followers, thereby improving the

output range of the device considerably with respect to conven-

tional op amps. The AD823 can drive 20 mA with the outputs

within 0.6 V of the supply rails. The AD823 also offers out-

standing precision for a high speed op amp. Input offset voltages

of 1 mV max and offset drift of 2 µV/°C are achieved through

the use of Analog Devices’ advanced thin-film trimming

techniques.

A “Nested Integrator” topology is used in the AD823 (see small-

signal schematic shown in Figure 36). The output stage can be

modeled as an ideal op amp with a single-pole response and a

unity-gain frequency set by transconductance gm2 and capacitor

C2. R1 is the output resistance of the input stage; gm is the in-

put transconductance. C1 and C5 provide Miller compensation

for the overall op amp. The unity gain frequency will occur at

gm/C5. Solving the node equations for this circuit yields:

VOUT =

A0

Vi

(

sR1[C1

(

A2

+

1)]

+

1)

×





s





gm2

C2





+

1

where:

A0 = gmgm2R2R1 (Open Loop Gain of Op Amp)

A2 = gm2R2 (Open Loop Gain of Output Stage)

VCC

R42

J1

VINP

VINN

R37

VBE + 0.3V V1

I5

Q43

Q44

Q55

I6

A=1

Q72

J6

S1P

Q61

Q46

Q58

Q49

R44 R28

Q18

C2

Q21

Q54

S1N

Q62

Q60

Q57

A=19

VOUT

I1

VEE

VCC

Q48

Q53

Q35

C6 R33

I2

R43

C1

VB

I3

Q56

Q52

I4

Q59

A=1

Q17

A=19

Figure 35. Simplified Schematic

REV. 0

–11–

Share Link: