80960MC(2004) 查看數據表（PDF） - Intel

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80960MC
(Rev.:2004)

EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT

Intel 

80960MC

EMBEDDED 32-BIT MICROPROCESSOR

WITH INTEGRATED FLOATING-POINT UNIT

AND MEMORY MANAGEMENT UNIT

Commercial

■ High-Performance Embedded Architecture ■ On-Chip Memory Management Unit

— 25 MIPS Burst Execution at 25 MHz

— 9.4 MIPS* Sustained Execution at

25 MHz

■ On-Chip Floating Point Unit

— Supports IEEE 754 Floating Point

Standard

— Full Transcendental Support

— Four 80-Bit Registers

— 13.6 Million Whetstones/s

(Single Precision) at 25 MHz

■ 512-Byte On-Chip Instruction Cache

— Direct Mapped

— Parallel Load/Decode for Uncached

Instructions

■ Multiple Register Sets

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored

On-Chip (Sixteen 32-Bit Registers per

Set)

— Register Scoreboarding

— 4 Gbyte Virtual Address Space per

Task

— 4 Kbyte Pages with Supervisor/User

Protection

■ Built-in Interrupt Controller

— 32 Priority Levels

— 248 Vectors

— Supports M8259A

— 3.4 µs Latency @ 25 MHz

■ Easy to Use, High Bandwidth 32-Bit Bus

— 66.7 Mbytes/s Burst

— Up to 16 Bytes Transferred per Burst

■ Multitasking and Multiprocessor Support

— Automatic Task dispatching

— Prioritized Task Queues

■ Advanced Package Technology

— 132-Lead Ceramic Pin Grid Array

FOUR

80-BIT FP

REGISTERS

80-BIT

FPU

SIXTEEN

32-BIT GLOBAL

REGISTERS

64- BY 32-BIT

LOCAL

REGISTER

CACHE

32-BIT

INSTRUCTION

EXECUTION

UNIT

MMU

INSTRUCTION

FETCH UNIT

512-BYTE

INSTRUCTION

CACHE

INSTRUCTION

DECODER

MICRO-

INSTRUCTION

SEQUENCER

MICRO-

INSTRUCTION

ROM

32-BIT

BUS CONTROL

LOGIC

32-BIT

BURST

BUS

Figure 1. The 80960MC Processor’s Highly Parallel Architecture

© INTEL CORPORATION, 2004

September, 2004

Order Number: 273123-002

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