74F50109 查看數據表（PDF） - Philips Electronics

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74F50109

Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics

Philips Electronics 

Philips Semiconductors

Synchronizing dual J–K positive edge-triggered

flip-flop with metastable immune characteristics

Product specification

74F50109

FEATURE

• Metastable immune characteristics

• Output skew guaranteed less than 1.5ns

• High source current (IOH = 15mA) ideal for clock driver

applications

• Pinout compatible with 74F109

• See 74F5074 for synchronizing dual D-type flip-flop

• See 74F50728 for synchronizing cascaded D-type flip-flop

• See 74F50729 for synchronizing dual D-type flip-flop with

edge-triggered set and reset

TYPE

74F50109

TYPICAL fmax

150MHz

TYPICAL SUPPLY

CURRENT( TOTAL)

22mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

16–pin plastic DIP

COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

N74F50109N

16–pin plastic SO

N74F50109D

PKG DWG #

SOT38-4

SOT109-1

INPUT AND OUTPUT LOADING

AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) LOAD

HIGH/

VALUE

LOW HIGH/LOW

J0, J1

J inputs

1.0/0.417 20µA/250µA

K0, K1

K inputs

1.0/0.417 20µA/250µA

CP0, CP1

Clock inputs

(active rising edge)

1.0/0.033

20µA/20µA

SD0, SD1

Set inputs

(active low)

1.0/0.033 20µA/20µA

RD0, RD1

Reset inputs

(active low)

1.0/0.033 20µA/20µA

Q0, Q1, Q0, Q1 Data outputs

750/33 15mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the high

state and 0.6mA in the low state.

PIN CONFIGURATION

RD0 1

J0 2

K0 3

CP0 4

SD0 5

Q0 6

Q0 7

GND 8

16 VCC

15 RD1

14 J1

13 K1

12 CP1

11 SD1

10 Q1

9 Q1

SF00598

LOGIC SYMBOL

2 14 3 13

4

CP0 J0 J1 K0 K1

5

SD0

1

RD0

12

CP1

11

SD1

15

RD1 Q0 Q0 Q1 Q1

VCC = Pin 16

GND = Pin 8

6 7 10 9

SF00599

IEC/IEEE SYMBOL

2

1J

4

C1

3

1K

1

R

5

S

14

2J

12

C2

13

2K

15

R

11

S

6

7

10

9

SF00600

September 14, 1990

2

853-1388 00422

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